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Примеры VHDL’2008
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1. Добавление конструкций языка PSL для проверки свойств модели
--------------------------------------------------------------------
-- 1. Добавление конструкций языка PSL для проверки свойств модели
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
entity Mealy is
port(x1, x2, x3, x4 : in std_logic;
clk, rst : in std_logic;
y1, y2, y3, y4, y5, y6 : out std_logic);
end Mealy;
architecture rtl of Mealy is
type T_state is (a1, a2, a3, a4, a5, a6);
signal NEXT_state, state : T_state;
signal w : std_logic_vector (1 to 6);
-- psl default clock is rising_edge(clk); -- VHDL'2008
-- psl property prop1 is
-- always {state = a2; NEXT_state = a3};
-- psl as1 : assert prop1;
-- psl as2 : assert always {state = a2; state = a4} |=> {state = a6};
-- psl as3 : cover {state = a1; state = a4};
-- psl as4 : assert always {state=a4} |=> {state=a5};
-- psl as5 : cover {state = a4; state = a5};
begin
y1 <= w(1);
y2 <= w(2);
y3 <= w(3);
y4 <= w(4);
y5 <= w(5);
y6 <= w(6); ns : process (state, x1, x2, x3, x4) begin case state is when a1 =>
NEXT_state <= a2; w <= "000101"; when a2 =>
if ((x1 and not x2 and not x3) or (x1 and x2)) = '1'
then NEXT_state <= a3; w <= "000000";
elsif ((x1 and not x2 and x3) = '1')
then NEXT_state <= a4; w <= "001000";
elsif (not x1 = '1')
then NEXT_state <= a5; w <= "000010"; end if; when a3 => NEXT_state <= a4; w <= "001001"; when a4 =>
if (not x2 = '1')
then NEXT_state <= a1; w <= "000000";
elsif (x2 = '1')
then NEXT_state <= a6; w <= "010000"; end if; when a5 =>
if ((not x1 and x4) = '1')
then NEXT_state <= a1; w <= "100000";
elsif ((not x4) or (x1 and x4)) = '1'
then NEXT_state <= a4; w <= "001001"; end if; when a6 => NEXT_state <= a1; w <= "100000";
end case;
end process ns;
p2 : process (clk, rst) is
begin -- process p2
if rst = '1' then -- asynchronous reset (active low)
state <= a1;
elsif clk'event and clk = '1' then -- rising clock edge
state <= NEXT_state;
end if;
end process p2;
end rtl; |
2. Параметризация типов и список параметров для пакетов
-------------------------------------------------------------------
-- 2. Параметризация типов и список параметров для пакетов
--------------------------------------------------------------------
package func_pkg is
generic (type element_type;
function "+" (
a : element_type;
b : element_type)
return element_type;
function "-" (
a : element_type;
b : element_type)
return element_type);
function add (a : element_type; b : element_type) return element_type;
function sub (a : element_type; b : element_type) return element_type;
end package func_pkg;
package body func_pkg is
function add (
a : element_type;
b : element_type)
return element_type is
begin -- function add
return a + b;
end function add;
function sub (
a : element_type;
b : element_type)
return element_type is
begin -- function add
return a - b;
end function sub;
end package body func_pkg;
---------------------------------
package func_int_pkg is new work.func_pkg
generic map (element_type => integer,
"+" => "+",
"-" => "-");
package func_real_pkg is new work.func_pkg
generic map (element_type => real,
"+" => "+",
"-" => "-");
---------------------------------
library ieee;
entity adder is
generic (type element_type;
function add (
a : element_type;
b : element_type)
return element_type);
port (
a, b : in element_type;
y : out element_type);
end entity adder;
architecture beh of adder is
begin -- architecture beh
y <= add(a, b); end architecture beh; --------------------------------- use work.func_int_pkg.all; use work.func_real_pkg.all; use std.env.all; entity test_tb is end entity test_tb; architecture beh of test_tb is component adder is generic ( type element_type; function add ( a : element_type; b : element_type) return element_type); port ( a, b : in element_type; y : out element_type); end component adder; signal a_int, b_int : integer := 1; signal y_int : integer; signal a_real, b_real : real := 1.0; signal y_real : real; begin -- architecture beh adder_int : adder generic map ( element_type => integer,
add => sub)
port map (
a => a_int,
b => b_int,
y => y_int);
adder_real : adder
generic map (
element_type => real,
add => add)
port map (
a => a_real,
b => b_real,
y => y_real);
a_int <=
a_int + 1 after 5 ns;
b_int <=
b_int + 1 after 50 ns;
a_real <=
a_real + 1.0 after 5 ns;
b_real <=
b_real + 1.0 after 50 ns;
process is
begin
wait for 1 us;
stop(1);
end process;
end architecture beh; |
3. Массивы с неограниченными диапазонами
-------------------------------------------------------------------
-- 3. Массивы с неограниченными диапазонами
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity prov_uncon_array is
end;
architecture beh of prov_uncon_array is
type std_logic_matrix is array (natural range <>) of std_logic_vector; -- VHDL'2008
signal A : std_logic_matrix(4 downto 0)(5 downto 0);
signal c1 : std_logic_matrix(0 to 6)(7 downto 0);
signal c2 : std_logic_matrix(5 downto 0)(2 to 4);
type std_logic_matrix_old is array (4 downto 0) of std_logic_vector (5 downto 0);
signal B : std_logic_matrix_old;
begin
process
begin
wait for 100 ns;
a <= ("111111",
"100000",
"010000",
"001000",
"000010");
wait for 100 ns;
b <= ("111111",
"100000",
"010000",
"001000",
"000111");
wait for 100 ns;
wait;
end process;
end beh; |
4. Записи с неограниченными массивами
-------------------------------------------------------------------
-- 4. Записи с неограниченными массивами
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity prov_record is
end;
architecture beh of prov_record is
type complex is record -- VHDL'2008
a : std_logic_vector;
b : signed;
d : natural range 0 to 10;
c : unsigned;
end record;
signal a1 : std_logic_vector (3 downto 0);
signal b1 : signed (1 to 5);
signal c1 : unsigned (6 downto 3);
signal X1 : complex (a (3 downto 0), b (1 to 5), c (6 downto 3));
-- пропускаем те поля, которые ограничены
begin
process
begin
wait for 100 ns;
-- X1<= ("1111", "10000", "0100");
X1.a <= "1111";
X1.b <= "10000";
X1.c <= "1010";
wait for 100 ns;
a1 <= x1.a;
b1 <= x1.b;
c1 <= x1.c;
wait for 100 ns;
wait;
end process;
end beh; |
5. Использование чисел с фиксированной точкой
-------------------------------------------------------------------
-- 5. Использование чисел с фиксированной точкой
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all; -- VHDL'2008
entity prov_fix_type is
end;
architecture beh of prov_fix_type is
signal a : ufixed (3 downto -3) := "0110100"; -- 6.5
signal b : ufixed (4 downto -2) := "0110001"; -- 12,25
signal c : ufixed (5 downto -3);
signal d : ufixed (5 downto -3);
signal e : ufixed (8 downto -5);
signal k : ufixed (5 downto -8);
begin
process(all)
begin
c <= a + b;
d <= b - a;
e <= a * b;
k <= a / b;
end process;
end beh; |
6. Использование чисел с плавающей точкой
-------------------------------------------------------------------
-- 6. Использование чисел с плавающей точкой
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all; -- VHDL'2008
entity prov_float_type is
end;
architecture beh of prov_float_type is
signal a : float (8 downto -23) := "01000001101000000000000000000000"; --+6.5
signal b : float (8 downto -23) := "01000000000000000000000000000000"; --+2.0
signal c, d, e, k, r : float (8 downto -23);
signal a_real : real;
signal b_real : real;
signal c_real : real;
signal d_real : real;
signal e_real : real;
signal k_real : real;
signal r_real : real;
begin
c <= a + b;
d <= b - a;
e <= a * b;
k <= a/b;
r <= b/a;
a_real <= to_real(a);
b_real <= to_real(b);
c_real <= to_real(c);
d_real <= to_real(d);
e_real <= to_real(e);
k_real <= to_real(k);
r_real <= to_real(r);
end beh;
-------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
entity prov_float is
end;
architecture beh of prov_float is
signal a, b : float (5 downto -6) := b"1_01111_010000"; -- число (-1.25)
signal c, d, e, k, r : float (5 downto -6);
signal a_real : real;
signal b_real : real;
signal c_real : real;
signal d_real : real;
signal e_real : real;
signal k_real : real;
signal r_real : real;
begin
c <= a + b;
d <= b - a;
e <= a * b;
k <= a/b;
r <= b/a;
a_real <= to_real(a); -- число (-1.25)
b_real <= to_real(b); -- число (-1.25)
c_real <= to_real(c); -- число (-2.5)
d_real <= to_real(d); -- число (0)
e_real <= to_real(e); -- число (1.5625)
k_real <= to_real(k); -- число (1)
r_real <= to_real(r); -- число (1)
end beh;
--------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all; -- VHDL'2008
entity prov_float_type is
end;
architecture beh of prov_float_type is
constant exp_width : natural := 8;
constant fract_width : natural := 13;
signal a : float (exp_width downto -fract_width); -- := "01000001101000000000000000000000"; -- +6.5
signal b : float (exp_width downto -fract_width); -- := "01000000000000000000000000000000"; -- +2.0
signal c : float (exp_width downto -fract_width);
signal d : float (exp_width downto -fract_width);
signal e : float (exp_width downto -fract_width);
signal k : float (exp_width downto -fract_width);
signal r : float (exp_width downto -fract_width);
signal a_real : real;
signal b_real : real;
signal c_real : real;
signal d_real : real;
signal e_real : real;
signal k_real : real;
signal r_real : real;
begin
process
begin
a <= to_float(6.5, exp_width, fract_width);
b <= to_float(2.0, exp_width, fract_width);
wait for 100 ns;
a <= to_float(10.0, exp_width, fract_width);
b <= to_float(5.0, exp_width, fract_width);
wait for 100 ns;
a <= to_float(10.0, exp_width, fract_width);
b <= to_float(3.0, exp_width, fract_width);
wait for 100 ns;
wait;
end process;
c <= a + b;
d <= b - a;
e <= a * b;
k <= a/b;
r <= b/a;
a_real <= to_real(a);
b_real <= to_real(b);
c_real <= to_real(c);
d_real <= to_real(d);
e_real <= to_real(e);
k_real <= to_real(k);
r_real <= to_real(r);
end beh; |
7. Иерархические ссылки на сигналы
-------------------------------------------------------------------
-- 7. Иерархические ссылки на сигналы
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
entity tstb is
end;
architecture BEHAVIOR of tstb is
component vlsi_1
port (a, b : in std_logic_vector (2 downto 1);
x : in std_logic;
D : out std_logic_vector (4 downto 1));
end component;
signal DATA : std_logic_vector (4 downto 0);
signal a, b : std_logic_vector (2 downto 1);
signal x : std_logic;
signal D : std_logic_vector (4 downto 1);
signal inter_sig_c1 : std_logic;
begin
p1 : vlsi_1 port map (a, b, x, D);
a <= (DATA(4), DATA(3));
b <= (DATA(2), DATA(1));
x <= DATA(0);
inter_sig_c1 <= << signal .tstb.p1.circ3.c1 : std_logic >>; -- VHDL'2008
process
file INFILE, OUTFILE : text;
variable PTR, POKE, PREA : line;
variable DATA_IN : std_logic_vector (4 downto 0);
variable DATA_OUT : std_logic_vector (4 downto 1);
begin
file_open(INFILE, "IN.TST", read_mode);
file_open(OUTFILE, "OUT.TST", write_mode);
while not (endfile(INFILE)) loop
wait for 20 ns;
readline(INFILE, PTR);
read(PTR, DATA_IN);
DATA <= DATA_IN;
wait for 20 ns;
DATA_OUT := D;
write(POKE, DATA_OUT);
writeline(OUTFILE, POKE);
end loop;
file_close(OUTFILE);
file_close(INFILE);
assert(false) report "Done!" severity warning;
wait;
end process;
end;
----------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vlsi_1 is
port (a, b : in std_logic_vector (2 downto 1);
x : in std_logic;
D : out std_logic_vector (4 downto 1));
end vlsi_1;
architecture str of vlsi_1 is
component
adder_2
port (a1, b1, a2, b2 : in std_logic;
c2, s2, s1 : out std_logic);
end component;
component mult_2
port(s1, s0, r1, r0 : in std_logic;
t3, t2, t1, t0 : out std_logic);
end component;
component YY_MUX
port (t4, t3, t2, t1, c2, s2, s1, x : in std_logic;
d4, d3, d2, d1 : out std_logic);
end component;
signal t4, t3, t2, t1, c2, s2, s1 : std_logic;
begin
circ1 : YY_MUX port map (t4, t3, t2, t1, c2, s2, s1, x,
d(4), d(3), d(2), d(1));
circ2 : mult_2
port map (a(2), a(1), b(2), b(1), t4, t3, t2, t1);
circ3 : adder_2
port map (a(2), a(1), b(2), b(1), c2, s2, s1);
end str;
--------------------------
library ieee;
use ieee.std_logic_1164.all;
entity adder_2 is
port (a1, b1, a2, b2 : in std_logic;
c2, s2, s1 : out std_logic);
end adder_2;
architecture struct_1 of adder_2 is
component
add1
port (b1, b2 : in std_logic;
c1, s1 : out std_logic);
end component;
component add2
port(c1, a1, a2 : in std_logic;
c2, s2 : out std_logic);
end component;
signal c1 : std_logic;
begin
circ1 : add1
port map (b1, b2, c1, s1);
circ2 : add2
port map (c1, a1, a2, c2, s2);
end struct_1; |
8. Фраза «all» для списка чувствительности процесса
-------------------------------------------------------------------
-- 8. Фраза «all» для списка чувствительности процесса
--------------------------------------------------------------------
entity example_selection is
port (x1, x2, x3, x4 : in bit;
selection : in bit_vector(1 downto 0);
F : out bit);
end example_selection;
architecture first_1993 of example_selection is
begin
process (x1, x2, x3, x4, selection) -- VHDL'1993
begin
case selection is
when "00" => F <= x1; when "01" => F <= x2; when "10" => F <= x3; when others => F <= x4; end case; end process; end first_1993; architecture second_2008 of example_selection is begin process (all) -- VHDL'2008 begin case selection is when "00" => F <= x1; when "01" => F <= x2; when "10" => F <= x3; when others => F <= x4;
end case;
end process;
end second_2008; |
9. Упрощенный оператор case (выбора)
--------------------------------------------------------------------
-- 9. Упрощенный оператор case (выбора)
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Encoder is
port (x, y : in std_logic_vector (1 downto 0);
F : out unsigned (3 downto 0));
end Encoder;
architecture beh of Encoder is
begin
process (x, y)
constant z : std_logic_vector (1 downto 0) := "10";
constant w1 : std_logic_vector (1 downto 0) := "10";
constant w2 : std_logic_vector (1 downto 0) := "11";
begin
case ((x xor y) & z) is
when "1010" => F <= "1000"; when w1 & w2 => F <= "0100"; when "001-" => F <= "0010"; when "1101" => F <= "0001"; when "01--" => F <= "1111"; when others => F <= "0110";
end case;
end process;
end beh; |
10. Безразличные условия в операторах case
--------------------------------------------------------------------
-- 10. Безразличные условия в операторах case
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Encoder is
port (x : in std_logic_vector (3 downto 0);
F : out unsigned (3 downto 0));
end Encoder;
architecture beh of Encoder is
begin
process (x)
begin
case? x is
when "10--" => F <= "1000"; when "01--" => F <= "0100"; when "001-" => F <= "0010"; when "0001" => F <= "0001"; when "11--" => F <= "1111"; when others => F <= "0000";
end case?;
end process;
end beh; |
11. Упрощенные условные выражения
-------------------------------------------------------------------
-- 11. Упрощенные условные выражения
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity prov_new_if is
end;
architecture beh of prov_new_if is
signal a : std_logic := '1';
signal b : std_logic := 'H';
signal c : std_logic := '1';
signal x1, x2, x3 : std_logic;
signal d : bit := '1';
signal e : bit := '0';
signal k : bit;
begin
process
begin
wait for 100 ns;
if (a or b) then
x1 <= '1';
else
x1 <= '0';
end if;
wait for 100 ns;
if (d and e) then
k <= '1';
else
k <= '0';
x2 <= '1';
end if;
wait for 100 ns;
if ((a or b) and (a or b ?= '1')) then
x3 <= (a or b ?= '1');
end if;
wait for 100 ns;
wait;
end process;
end beh; |
12. Чтение выходных портов
-------------------------------------------------------------------
-- 12. Чтение выходных портов
--------------------------------------------------------------------
entity out_port is
port(
x1, x2, x3 : in bit;
y1, y2 : out bit);
end out_port;
architecture beh of out_port is
begin
y1 <= (x1 and x2);
y2 <= (x1 xor x3) or y1; -- y1 выходной порт
end beh; |
13. Унарная редукция логических операторов
-------------------------------------------------------------------
-- 13. Унарная редукция логических операторов
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity prov_unary_reduction is
end;
architecture beh of prov_unary_reduction is
constant a : signed (1 to 4) := "0111";
signal b, c, d, e, f, g : std_logic;
begin
process
begin
wait for 100 ns;
b <= and (a); -- b <= a(1) and a(2) and a(3) and a(4);
c <= nand (a); -- c <= not ( a(1) and a(2) and a(3) and a(4) );
d <= or (a); -- d <= a(1) or a(2) or a(3) or a(4);
e <= nor (a); -- e <= not ( a(1) or a(2) or a(3) or a(4) );
f <= xor (a); -- f <= a(1) xor a(2) xor a(3) xor a(4);
g <= xnor (a); -- g <= a(1) xnor a(2) xnor a(3) xnor a(4);
wait;
end process;
end beh; |
14. Изменения в пакете STANDARD библиотеки STD
--------------------------------------------------------------------
-- 14. Изменения в пакете STANDARD библиотеки STD
--------------------------------------------------------------------
entity std_tb is
end entity std_tb;
architecture beh of std_tb is
signal bv : bit_vector(3 downto 0) := 4d"12";
signal r : real := 1.0045;
signal int : integer := 10045;
signal bool : boolean := true;
begin -- architecture beh
p1 : process is
begin -- process p1
report "Bit_vector = " & to_string(bv) & " O = " & to_ostring(bv) & " HEX = " & to_hstring(bv) & LF severity note;
report "Real = " & to_string(r) & " ""%6.3f"" = " & to_string(r, "%6.3f") & LF severity note;
report "Integer = " & to_string(int) & LF severity note;
report "Boolean = " & to_string(bool) & LF severity note;
wait;
end process p1;
end architecture beh; |
15. Изменения в пакете TEXTIO библиотеки STD
-------------------------------------------------------------------
-- 15. Изменения в пакете TEXTIO библиотеки STD
--------------------------------------------------------------------
use std.textio.all;
entity textio_tb is
generic (
filename : string := "./file.log");
end entity textio_tb;
architecture beh of textio_tb is
signal bv : bit_vector(3 downto 0) := 4d"12";
signal r : real := 1.0045;
signal int : integer := 10045;
signal bool : boolean := true;
file outfile : text open write_mode is filename;
file infile : text open read_mode is filename;
begin -- architecture beh
p1 : process is
variable l : line;
begin -- process p1
write (l, "Bit_vector = " & to_string(bv) & " O = " & to_ostring(bv) & " HEX = " & to_hstring(bv) & LF);
write (l, "Real = " & to_string(r) & " ""%6.3f"" = " & to_string(r, "%6.3f") & LF);
STRING_WRITE(l, "Real = ");
write (l, r);
swrite (l, " ""%6.3f"" = ");
write (l, r, "%6.3f");
write (l, LF);
write (l, "Integer = " & to_string(int) & LF);
write (l, "Boolean = " & to_string(bool) & LF);
tee(outfile, l);
flush(outfile);
wait;
end process p1;
end architecture beh; |
16. Упрощенная запись символьных строк
--------------------------------------------------------------------
-- 16. Упрощенная запись символьных строк
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bit_str_tb is
end;
architecture beh of bit_str_tb is
-- vhdl'2008
signal s1 : std_logic_vector (1 to 12) := O"3XZ4";
signal ps1 : std_logic_vector (1 to 12) := "011XXXZZZ100";
signal s2 : std_logic_vector (1 to 16) := X"A3--";
signal ps2 : std_logic_vector (1 to 16) := "10100011--------";
signal s3 : std_logic_vector (1 to 5) := 5B"10UU";
signal ps3 : std_logic_vector (1 to 5) := "010UU";
signal s4 : std_logic_vector (1 to 6) := O"3_X";
signal ps4 : std_logic_vector (1 to 6) := "011XXX";
signal s5 : string(1 to 20) := 20SX"F#?F";
signal ps5 : string(1 to 20) := "11111111####????1111";
signal s6 : std_logic_vector(1 to 7) := 7X"3C";
signal ps6 : std_logic_vector(1 to 7) := "0111100";
signal s7 : std_logic_vector (1 to 8) := 8O"5";
signal ps7 : std_logic_vector (1 to 8) := "00000101";
signal s8 : std_logic_vector(1 to 10) := 10B"X";
signal ps8 : std_logic_vector(1 to 10) := "000000000X";
-- signal s9 : std_logic_vector(1 to 6):= 6X"FC"; -- Error
signal ps9 : std_logic_vector(1 to 6) := "111100";
begin
end architecture beh; |
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