Синтез логических схем – листинг


 

Содержание:

Глава 1. Теоретические основы синтеза логических cхем
1.1. VHDL – язык проектирования цифровых систем
1.2. Высокоуровневый синтез
1.3. Логический синтез
1.3.1. Булевы функции. Формы представления систем булевых функций
1.3.2. Базис синтеза
1.3.3. Задача синтеза комбинационной логической схемы и основные этапы ее решения
1.3.4. Оптимизация двухуровневых представлений
1.3.5. Оптимизация многоуровневых представлений
1.3.6. Технологическое отображение
1.4. Повторный синтез

Глава 2. Основные элементы языка VHDL
2.1. Лексические элементы и типы данных
2.1.1. Лексические элементы, разделители, операторы
2.1.2. Идентификаторы
2.1.3. Зарезервированные слова
2.1.4. Литералы
2.1.5. Типы
2.1.6. Подтипы, конверсия типов
2.2. Декларации
2.2.1. Упрощенная форма задания синтаксических конструкций языка VHDL
2.2.2. Декларация константы
2.2.3. Декларация переменной
2.2.4. Декларация сигнала
2.2.5. Декларация компонента
2.3. Интерфейс и архитектура объекта
2.4. Атрибуты
2.5. Имена
2.6. Операторы
2.7. Сигналы
2.8. Последовательные операторы
2.8.1. Оператор присваивания значения переменной
2.8.2. Назначение сигнала
2.8.3. Оператор if
2.8.4. Оператор case
2.8.5. Оператор loop
2.8.6. Оператор next
2.8.7. Оператор exit
2.8.8. Оператор null
2.8.9. Оператор вызова процедуры
2.8.10. Оператор return
2.8.11. Оператор assert
2.8.12. Оператор wait
2.9. Параллельные операторы
2.9.1. Оператор process
2.9.2. Оператор параллельного сообщения
2.9.3. Оператор параллельного вызова процедуры
2.9.4. Оператор условного назначения сигнала
2.9.5. Оператор выборочного назначения сигнала
2.9.6. Оператор конкретизации компонента
2.9.7. Оператор generate
2.9.8. Оператор block

Глава 3. Организация описания цифровой системы на языке VHDL
3.1. Функции
3.2. Процедуры
3.3. Пакеты
3.4. Библиотеки VHDL-описаний
3.5. Конфигурации. Стили VHDL-описаний
3.6. Моделирование VHDL-описаний

Глава 4. Синтез схем по описаниям на языке VHDL
4.1. Синтез схем по VHDL-описаниям. Сходство и различие систем моделирования и синтеза
4.2. Понятие синтезируемого подмножества языка VHDL
4.3. Типы входных, выходных данных после синтеза (std_logic, std_logic_vector)
4.4. Целевая библиотека синтеза
4.5. Кодирование данных при синтезе
4.5.1. Кодирование данных типа bit, bit_vector
4.5.2. Кодирование данных типа std_logic, std_logic_vector
4.5.3. Кодирование данных типа std_ulogic, std_ulogic_vector
4.5.4. Кодирование данных типа integer
4.5.5. Кодирование данных перечислимого типа
4.5.6. Кодирование данных типа array
4.5.7. Кодирование данных типа character
4.5.8. Кодирование строковых литералов
4.5.9. Кодирование данных типа record
4.6. Синтезируемые и несинтезируемые операторы и конструкции
4.6.1. Использование констант в логических выражениях
4.6.2. Использование переменных в логических выражениях
4.6.3. Общие переменные
4.6.4. Логические операторы над типом std_logic
4.6.5. Арифметические операторы
4.6.6. Оператор if
4.6.7. Использование констант в арифметических выражениях
4.6.8. Оператор case
4.6.9. Оператор цикла
4.6.10. Выходной порт нельзя использовать в выражениях
4.6.11. Оператор assert
4.6.12. Оператор wait
4.6.13. Операторы сдвига
4.6.14. Оператор generate
4.6.15. Использование изменяемых параметров (generic)
4.6.16. Оператор конкретизации компонента
4.6.17. Инициализация внутренних сигналов схемы
4.6.18. Начальное значение порта игнорируется
4.6.19. Использование глобальных сигналов
4.6.20. Оператор вызов функции
4.6.21. Схемная реализация разрешающей функции
4.6.22. Переименования (alias)
4.6.23. Схемная реализация атрибутов
4.6.24. Группы
4.6.25. Типы сигналов register и bus. Охраняемый блок
4.6.26. Охраняемые сигналы
4.6.27. Тип real не поддерживается при синтезе
4.6.28. Оператор назначения сигнала
4.6.29. Перегрузка операторов (overload)
4.6.30. Алгоритмические конструкции, переводящиеся при синтезе в элементы памяти и буферы
4.7. Синтезируемые описания комбинационных схем
4.7.1. Таблицы истинности (совершенные ДНФ)
4.7.2. Системы ДНФ
4.7.3. Многоуровневые и полиномиальные представления
4.7.4. Диаграммы двоичного решения (BDD)
4.8. Синтезируемые описания конечных автоматов
4.8.1. Конечный автомат
4.8.2. Микропрограммный автомат
4.9. Синтез типовых схем
4.9.1. Генератор синхросигналов
4.9.2. Дешифратор
4.9.3. Мультиплексор
4.9.4. Демультиплексор
4.9.5. Постоянное запоминающее устройство
4.9.6. Двухразрядный сумматор
4.9.7. Четырехразрядный сумматор
4.9.8. Многоразрядный сумматор
4.9.9. Двухразрядный умножитель
4.9.10. Инкрементор, декрементор
4.9.11. Компаратор
4.9.12. Программируемая логическая матрица
4.9.13. D-триггер
4.9.14. Параллельный регистр
4.9.15. Сдвиговый регистр
4.9.16. Счетчик
4.10. Управление синтезом
4.10.1. Установление опций автоматического синтеза
4.10.2. Смена стилей описания схемы
4.10.3. Использование конфигураций
4.10.4. Использование “черных ящиков”
4.11. Повторный синтез
4.12. Исследование эффективности алгоритмов синтеза системы Leonardo

Литература

Предметный указатель

 

 


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Глава 1. Теоретические основы синтеза логических cхем
1.2. Высокоуровневый синтез

entity adder_2 is
  port(A, B : in  integer range 0 to 3;
        C   : out integer range 0 to 6);
end adder_2;
architecture functional of adder_2 is
begin
  C <= A + B;
end functional;

entity vlsi_1f is
  port (a, b : in  integer range 0 to 3;
        x    : in  bit;
        D    : out integer range 0 to 9);
end vlsi_1f;
 
architecture functional of vlsi_1f is
 
begin
  po : process(a, b, x)
    variable e : integer range 0 to 9;
  begin
    if (x = '0') then
      e := a + b;
    elsif (x = '1') then
      e := a * b;
    end if;
    D <= e;
  end process;
 
end functional;

entity vlsi is
  port (a, b : in  integer range 1 to 4;
        D    : out integer range -1 to 8);
end vlsi;
 
architecture functional_1 of vlsi is
  signal v : integer range 2 to 8;
  signal w : integer range 1 to 16;
begin
  addition : process(a, b)
  begin
    v <= a + b;
  end process;
  multiplication : process(a, b)
  begin
    w <= a * b;
  end process;
  D <= w - v;
end functional_1;

entity vlsi is
  port (a, b : in  integer range 1 to 4;
        D    : out integer range -1 to 8);
end vlsi;
 
architecture functional_2 of vlsi is
 
begin
  add_mult : process (a, b)
    variable v : integer range 2 to 8;
    variable w : integer range 1 to 16;
  begin
    v := a+b;
    w := a*b;
    D <= w - v;
  end process;
end functional_2;

entity vlsi is
  port (a, b : in  integer range 1 to 4;
        D    : out integer range -1 to 8);
end vlsi;
 
architecture functional_3 of vlsi is
begin
  D <= (a*b) - (a+b);
end functional_3;

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Глава 2. Основные элементы языка VHDL
2.3. Интерфейс и архитектура объекта

entity ANDOR is
  port (x1, x2, x3 : in  bit;
        f          : out bit);
end ANDOR;
 
architecture RTL1 of ANDOR is
begin
  f <= (x1 and x2) or x3;
end RTL1;
 
architecture RTL2 of ANDOR is
  signal w : bit;
begin
  w <= x1 and x2;
  p1 : process (w, x3)
  begin
    f <= w or x3;
  end process p1;
end RTL2;

entity Cate is
  generic
    (N : natural := 4);
  port
    (Inputs : in  bit_vector (1 to N);
     Result : out bit);
end Cate;

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2.4. Атрибуты

entity signal_ex is
end signal_ex;
 
architecture beh of signal_ex is
  signal ex, y1, y3 : bit;
  signal y2         : boolean;
begin
  ex <= '0' after 20 ns,
        '1' after 50 ns,
        '0' after 60 ns,
        '1' after 80 ns;
  y1 <= ex'transaction;
  y2 <= ex'event;
  y3 <= ex'last_value;
end beh;

entity test_attr_vector is
end test_attr_vector;
 
architecture beh of test_attr_vector is
 
  type vector is array (7 downto 0) of bit;
  signal x          : vector;
  signal A, B, C, D : integer;
  signal E          : boolean;
  signal F, G, H    : integer;
 
begin
  A <= vector'left;
  B <= vector'right;
  C <= vector'low;
  D <= vector'high;
  F <= vector'range;
  G <= vector'reverse_range;
  H <= vector'length;
end beh;

entity test_attr_scalar is
end test_attr_scalar;
 
architecture beh of test_attr_scalar is
 
  type new_values is (a1, b1, a2, b2, a3, b3, w);
 
  signal A, B, C, D    : new_values;
  signal H             : integer;
  signal K, L, M, N, P : new_values;
begin
  A <= new_values'left;
  B <= new_values'right;
  C <= new_values'low;
  D <= new_values'high;
  H <= new_values'pos(b3);
  K <= new_values'val(2);
-- L <= new_values'succ(w);   bad
  L <= new_values'succ(b3);
  M <= new_values'pred(b2);
--  N <= new_values'leftof(a1);   bad
  N <= new_values'leftof(b1);
--  P <= new_values'rightof(w);    bad
  P <= new_values'rightof(b3);
end beh;

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2.7. Сигналы

entity ANDOR is
  port(x1, x2, x3 : in  bit;
        f         : out bit);
end ANDOR;
architecture example of ANDOR is
  signal w : bit;
begin
  p0 : w <= x1 and x2 after 10 ns;
  p1 : process (w, x3)
  begin
    f <= w or x3 after 20 ns;
  end process p1;
end example;

entity ANDOR is
  port(x1, x2, x3 : in  bit;
        f         : out bit);
end ANDOR;
 
architecture DELTA of ANDOR is
  signal w : bit;
begin
  p0 : w <= x1 and x2;                  -- нет слова after
  p1 : process(w, x3)
  begin
    f <=w or x3;                        -- нет слова after
  end process p1;
end DELTA;

entity vlsi_postponed is
  port (a, b : in  integer range 1 to 4;
        D    : out integer range -16 to 16);
end vlsi_postponed;
architecture func of vlsi_postponed is
  signal v : integer range 1 to 8;
  signal w : integer range 1 to 16;
begin
  addition : process(a, b)
  begin
    v <= a + b;
  end process;
  multiplication : postponed process (a, b)
                            -- отложенный процесс
                            begin
                              w <= a * b;
                            end process;
                            D <= w - v;
                            end func;

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2.8.1. Оператор присваивания значения переменной

entity VAR is
end VAR;
 
architecture functional of VAR is
  signal A, B, J : bit_vector(1 downto 0);
  signal E, F, G : bit;
begin
  p0 : process (A, B, E, F, G, J)
    variable C, D, H, Y : bit_vector(1 downto 0);
    variable W, Q       : bit_vector(3 downto 0);
    variable Z          : bit_vector(0 to 7);
    variable X          : bit;
    variable DATA       : bit_vector(31 downto 0);
  begin
    C         := "11";
    X         := E and F;
    Y         := H nand J;
    Z(0 to 3) := C & D;                                      --  конкатенация
    Z(4 to 7) := (not A) & (A nor B);                        --  конкатенация
    D         := ('0', '0');                                 --  агрегат
    W         :=(2 downto 1 => G, 3 => '1', others => '0');  --  агрегат
    22 DATA   := (others    => '1');                         --  агрегат
    23 end process;
    24 end functional;

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2.8.9. Оператор вызова процедуры

entity CALL_PRO is
end CALL_PRO;
architecture RTL of CALL_PRO is
  function bit_bool (inp_bit : in bit) return boolean is
  begin
    if (inp_bit = '1') then
      return true;
    else
      return false;
    end if;
  end bit_bool;
 
  procedure left_one (
    signal DATA  : in  bit_vector (1 to 8);
    signal l_bit : out integer) is
    variable temp : integer;
  begin
    temp := 0;
    for i in 1 to 8 loop
      if (DATA(i) = '1') then
        temp := i;
      end if;
      if (temp /= 0) then exit;
      end if;
    end loop;
    l_bit <= temp;
  end left_one;
 
  signal DIN    : bit_vector (1 to 8);
  signal bit_1  : bit;
  signal bool_1 : boolean;
  signal DOUT   : integer;
begin
  p0 : process (bit_1, DIN)
  begin
    bool_1 <= bit_bool(bit_1);          --  вызов функции
    LEFT_ONE(DIN, DOUT);                --  вызов процедуры
  end process;
  p1 : process
  begin
    bit_1 <= '1'        after 20 ns, '0' after 40 ns;
    DIN   <= "01010000" after 20 ns,
           "00000000" after 40 ns,
           "00001100" after 60 ns,
           "00000001" after 80 ns;
    wait for 100 ns;
  end process;
 
end RTL;

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2.9.4. Оператор условного назначения сигнала

entity example_condition is
  port (
    x1, x2, x3, x4 : in  bit;
    condition      : in  bit_vector(1 downto 0);
    F              : out bit);
end example_condition;
architecture first of example_condition is
begin
  F <= x1 when condition = "00" else
       x2 when condition = "01" else
       x3 when condition = "10" else
       x4;
end first;
architecture second of example_condition is
begin
  process (x1, x2, x3, x4, condition)
  begin
    if (condition = "00") then F    <= x1;
    elsif (condition = "01") then F <= x2;
    elsif (condition = "10") then F <= x3;
    else F                          <= x4;
    end if;
  end process;
end second;

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2.9.5. Оператор выборочного назначения сигнала

entity example_selection is
  port (x1, x2, x3, x4 : in  bit;
         selection     : in  bit_vector(1 downto 0);
         F             : out bit);
end example_selection;
architecture first of example_selection is
begin
  with selection select
    F <= x1 when "00",
    x2      when "01",
    x3      when "10",
    x4      when others;
end first;
architecture second of example_selection is
begin
  process (x1, x2, x3, x4, selection)
  begin
    case selection is
      when "00"   => F <= x1;
      when "01"   => F <= x2;
      when "10"   => F <= x3;
      when others => F <= x4;
    end case;
  end process;
end second;

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2.9.6. Оператор конкретизации компонента

entity circuit1 is
  port (y, c, b, x1 : in  bit;
        a           : out bit);
end circuit1;
architecture struct_1 of circuit1 is
  component nao22
    port (a, b, c, d : in  bit;
          y          : out bit);
  end component;
  component nao2
    port (a, b, c : in  bit;
          y       : out bit);
  end component;
 
  signal w, d : bit;
begin
  m_3 : nao2
    port map (b => y, y => A, c => d, a => w);
  met1 : nao22
    port map (a => Y, b => C, c => b, D => x1, y => w);
  met2 : NAO22 port map (y, b, c, c, d);
end struct_1;
 
entity nao2 is
  port (a, b, c : in  bit;
        y       : out bit);
end nao2;
architecture beh_1 of nao2 is
begin
  y <= (not a) or (not b and not c);
end beh_1;
 
entity nao22 is
  port (a, b, c, d : in  bit;
        y          : out bit);
end nao22;
architecture beh_2 of nao22 is
begin
  y <= (not a and not b) or (not c and not d);
end beh_2;

entity nao22 is
  port (a, b, c, d : in  bit;
        y          : out bit);
end nao22;
architecture beh_2 of nao22 is
begin
  y <= (not a and not b) or (not c and not d);
end beh_2;

entity nao2 is
  port (a, b, c : in  bit;
        y       : out bit);
end nao2;
architecture beh_1 of nao2 is
begin
  y <= (not a) or (not b and not c);
end beh_1;

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2.9.7. Оператор generate

entity mp_vour is
  generic (N : natural := 4);
  port (x  : in  bit_vector (0 to 2*N);
        u8 : out bit);
end mp_vour;
architecture gomain of mp_vour is
  component xor2
    port (x1, x2 : in  bit;
          y      : out bit);
  end component;
  component nand2
    port (x1, x2 : in  bit;
          y      : out bit);
  end component;
  signal ss : bit_vector (0 to 2*N);
begin
  ss(0) <= x(0);
  g4 : for i in 1 to N generate
    gn : nand2 port map (x1 => ss(2*(i-1)), x2 => x(2*i-1), y => ss(2*i-1));
    gx : xor2 port map (x1  => ss(2*i-1), x2 => x(2*i), y => ss(2*i));
  end generate g4;
  u8 <= ss (2*N);
end gomain;
 
entity nand2 is
  port (x1, x2 : in  bit;
        y      : out bit);
end nand2;
architecture struct of nand2 is
begin
  y <= x1 nand x2;
end struct;
 
entity xor2 is
  port (x1, x2 : in  bit;
        y      : out bit);
end xor2;
architecture struct of xor2 is
begin
  y <= x1 xor x2;
end struct;

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2.9.8. Оператор block

entity add1_e is
  port (b1, b2, enable : in  bit;
        c1, s1         : out bit);
end add1_e;
architecture struct_3 of add1_e is
begin
  p0 : block (enable = '1')
  begin
    s1 <= guarded (b1 xor b2);
    c1 <= guarded (b1 and b2);
  end block p0;
end struct_3;

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Глава 3. Организация описания цифровой системы на языке VHDL
3.1 Функции

function bit_bool (inp_bit : in bit) return boolean is
begin
  if (inp_bit = '1') then
    return true;
  else
    return false;
  end if;
end bit_bool;

function BOOL_TO_SL(X : boolean)
  return std_ulogic is
begin
  if X then
    return '1';
  else
    return '0';
  end if;
end BOOL_TO_SL;

function PARITY (X : std_ulogic_vector)
  return std_ulogic is
  variable TMP : std_ulogic := '0';
begin
  for J in X'range loop
    TMP := TMP xor X(J);
  end loop;
  return TMP;
end PARITY;

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3.2. Процедуры

procedure PARITY
  (signal X : in  std_ulogic_vector;
   signal Y : out std_ulogic) is
  variable TMP : std_ulogic := '0';
begin
  for J in X'range loop
    TMP := TMP xor X(J);
  end loop;
  Y <= TMP;                             -- в процедуре могут быть операторы 
--  назначения сигналов
end PARITY;

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3.3. Пакеты

package vv_vls is
  function bin2_to_int (signal w2, w1 : bit)
    return integer;
  function int_to_bin4
    (signal INPUT : integer)
    return bit_vector;
  constant N                    : integer := 4;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer;
  type in_array is array (natural range 1 to 4,
                          natural range 1 to 4)  -- двумерный массив
    of integer range 0 to 7;
  type out_array is array (natural range 1 to 4,
                           natural range 1 to 4)
    of integer range 0 to 256;
 
  type fsm_in_type is (z1, z2);         -- перечислимый тип
  type fsm_out_type is (w1, w2, w3, w4);
  type states is (a1, a2);
end vv_vls;
 
package body vv_vls is                  -- тело пакета
  function bin_to_int                   -- функция
    (signal x    : bit_vector (0 to N-1))
    -- левый разряд старший, возрастающий диапазон
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function bin2_to_int                  -- функция
    (signal w2, w1 : bit)               --  w2 - старший разряд
    return integer is
    variable sum   : integer := 0;
  begin
    if w1 = '1' then
      sum := 1;
    else
      sum := 0;
    end if;
    if w2 = '1' then
      sum := sum+2;
    else
      sum := sum;
    end if;
    return sum;
  end bin2_to_int;
 
  function int_to_bin4                  -- функция
    (signal INPUT   : integer)
    return bit_vector is                -- правый разряд старший
    -- возрастающий диапазон
    variable fout   : bit_vector(0 to 3);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 3 downto 0 loop
      temp_b := temp_a/(2**i);
      temp_a := temp_a rem (2**i);
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_to_bin4;
 
end vv_vls;

наверх

3.4. Библиотеки VHDL-описаний

entity circuit1 is
  port (y, c, b, x1 : in  bit;
        a           : out bit);
end circuit1;
architecture struct_2 of circuit1 is
-- component nao22 
-- port (a, b, c, d : in bit; y : out bit);
-- end component;
-- component nao2 
-- port (a, b, c : in bit; y : out bit);
-- end component;
 
  signal w, d : bit;
begin
  m_3 : entity work.nao2(beh_1)
    port map (b => y, y => A, c => d, a => w);
  met1 : entity work.nao22(beh_2)
    port map (a => Y, b => C, c => b, D => x1, y => w);
  met2 : entity work.NAO22(beh_2)
    port map (y, b, c, c, d);
end struct_2;

entity nao22 is
  port (a, b, c, d : in  bit;
        y          : out bit);
end nao22;
architecture beh_2 of nao22 is
begin
  y <= (not a and not b) or (not c and not d);
end beh_2;

entity nao2 is
  port (a, b, c : in  bit;
        y       : out bit);
end nao2;
architecture beh_1 of nao2 is
begin
  y <= (not a) or (not b and not c);
end beh_1;

наверх

3.5. Конфигурации. Стили VHDL-описаний

entity add1 is
  port (b1, b2 : in  bit;
        c1, s1 : out bit);
end add1;
 
architecture struct_1 of add1 is
begin
  s1 <= ((b1 and (not b2)) or ((not b1) and b2));
  c1 <= b1 and b2;
end struct_1;
 
architecture struct_2 of add1 is
begin
  s1 <= b1 xor b2;
  c1 <= b1 and b2;
end struct_2;

entity add2 is
  port (c1, a1, a2 : in  bit;
        c2, s2     : out bit);
end add2;
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and a1 and (not a2)) or
        (c1 and (not a1)and (not a2)) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

entity adder_2 is
  port (a1, b1, a2, b2 : in  bit;
        c2, s2, s1     : out bit);
end adder_2;
 
architecture struct_1 of adder_2 is
  component
    add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
  component add2
    port(c1, a1, a2 : in  bit;
         c2, s2     : out bit);
  end component;
  signal c1 : bit;
 
begin
  circ1 : add1
    port map (b1, b2, c1, s1);
  circ2 : add2
    port map (c1, a1, a2, c2, s2);
end struct_1;

library ieee;
use ieee.std_logic_1164.all;
library work;
entity comp_3 is
  port (signal a, b        : in  integer range 0 to 3;
         signal EQ, LT, GT : out std_ulogic);
end comp_3;
architecture str of comp_3 is
  component compare
    port (a, b : in  integer range 0 to 3;
           EQ  : out std_ulogic);
  end component;
begin
  COMP1 : compare port map (A, B, EQ);
  COMP2 : compare port map (A, B, LT);
  COMP3 : compare port map (A, B, GT);
end str;

library ieee;                           -- Прочитать библиотеку
use ieee.std_logic_1164.all;
-- Сделать библиотеку "видимой"
entity compare is
  port(A, B : in  integer range 0 to 3;
       EQ   : out std_ulogic);
end compare;
 
architecture eq1 of compare is
begin
  EQ <= '1' when (A = B) else '0';
end eq1;
 
architecture lt1 of compare is
begin
  EQ <= '1' when (A < B) else '0';
end lt1;
 
architecture gt1 of compare is
begin
  EQ <= '1' when (A > B) else '0';
end gt1;

configuration config_1_adder_2 of adder_2 is
  for struct_1
    for all : add1
      use entity work.add1(struct_1);
    -- use entity work.add1(struct_2);
    end for;
    for all : add2
      use entity work.add2(struct_1);
    end for;
  end for;
end config_1_adder_2;

library work;
configuration default_configuration of comp_3 is
  for str
    for COMP1 : compare use entity work.compare (eq1);
    end for;
    for COMP2 : compare use entity work.compare (lt1);
    end for;
    for COMP3 : compare use entity work.compare (gt1);
    end for;
  end for;
end;

наверх

3.6. Моделирование VHDL-описаний

entity add1 is
  port (b1, b2 : in  bit;
        c1, s1 : out bit);
end add1;
 
architecture struct_1 of add1 is
begin
  s1 <= ((b1 and (not b2)) or ((not b1) and b2));
  c1 <= b1 and b2;
end struct_1;
 
architecture struct_2 of add1 is
begin
  s1 <= b1 xor b2;
  c1 <= b1 and b2;
end struct_2;

entity add2 is
  port (c1, a1, a2 : in  bit;
        c2, s2     : out bit);
end add2;
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and a1 and (not a2)) or
        (c1 and (not a1)and (not a2)) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

entity adder_2 is
  port (a1, b1, a2, b2 : in  bit;
        c2, s2, s1     : out bit);
end adder_2;
 
architecture struct_1 of adder_2 is
  component
    add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
  component add2
    port(c1, a1, a2 : in  bit;
         c2, s2     : out bit);
  end component;
  signal c1 : bit;
 
begin
  circ1 : add1
    port map (b1, b2, c1, s1);
  circ2 : add2
    port map (c1, a1, a2, c2, s2);
end struct_1;

entity mult_2 is
  port (s1, s0, r1, r0 : in  bit;
        t3, t2, t1, t0 : out bit);
end mult_2;
 
architecture struct of mult_2 is
  component
    add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
 
  signal p1, p2, p3, p4 : bit;
begin
  t0 <= r0 and s0;
  p2 <= r0 and s1;
  p1 <= r1 and s0;
  p4 <= r1 and s1;
 
  circ1 : add1
    port map (b1 => p1, b2 => p2, c1 => p3, s1 => t1);
  circ2 : add1
    port map (b1 => p3, b2 => p4, c1 => t3, s1 => t2);
end struct;

package vv_vls is
  function bin2_to_int (signal w2, w1 : bit)
    return integer;
  function int_to_bin4
    (signal INPUT : integer)
    return bit_vector;
  constant N                    : integer := 4;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer;
  type in_array is array (natural range 1 to 4,
                          natural range 1 to 4)  -- двумерный массив
    of integer range 0 to 7;
  type out_array is array (natural range 1 to 4,
                           natural range 1 to 4)
    of integer range 0 to 256;
 
  type fsm_in_type is (z1, z2);         -- перечислимый тип
  type fsm_out_type is (w1, w2, w3, w4);
  type states is (a1, a2);
end vv_vls;
 
package body vv_vls is                  -- тело пакета
  function bin_to_int                   -- функция
    (signal x    : bit_vector (0 to N-1))
    -- левый разряд старший, возрастающий диапазон
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function bin2_to_int                  -- функция
    (signal w2, w1 : bit)               --  w2 - старший разряд
    return integer is
    variable sum   : integer := 0;
  begin
    if w1 = '1' then
      sum := 1;
    else
      sum := 0;
    end if;
    if w2 = '1' then
      sum := sum+2;
    else
      sum := sum;
    end if;
    return sum;
  end bin2_to_int;
 
  function int_to_bin4                  -- функция
    (signal INPUT   : integer)
    return bit_vector is                -- правый разряд старший
    -- возрастающий диапазон
    variable fout   : bit_vector(0 to 3);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 3 downto 0 loop
      temp_b := temp_a/(2**i);
      temp_a := temp_a rem (2**i);
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_to_bin4;
 
end vv_vls;

library work;
use work.vv_vls.all;
 
entity test_VLSI_1 is
end test_VLSI_1;
 
architecture test of test_vlsi_1 is
  component vlsi_1
    port (a2, a1, b2, b1, x : in  bit;
          d4, d3, d2, d1    : out bit);
  end component;
 
 
  signal a2, a1, b2, b1, x, d4, d3, d2, d1 : bit;
  signal s                                 : bit_vector (0 to 3);
begin
  p : vlsi_1
    port map (a2 => a2, a1 => a1, b2 => b2, b1 => b1, x => x,
              d4 => d4, d3 => d3, d2 => d2, d1 => d1);
 
  a2 <= '1' after 25 ns; a1 <= '0' after 25 ns;
  b2 <= '1' after 25 ns; b1 <= '1' after 25 ns;
  x  <= '0' after 25 ns;
  s  <= (d4, d3, d2, d1);
  step1 : process (s)
    variable number : integer range 0 to 15;
  begin
    number := bin_to_int(s);
    if (number /= 5) then
      assert false report "bad (2+3/=5)" severity error;
    end if;
    if (number = 5) then
      assert false report "good (2+3=5)" severity warning;
    end if;
  end process;
end test;

entity VLSI_1 is
  port (a2, a1, b2, b1, x : in  bit;
        d4, d3, d2, d1    : out bit);
end VLSI_1;
 
architecture structure of vlsi_1 is
 
  component
    adder_2
    port (a1, b1, a2, b2 : in  bit;
          c2, s2, s1     : out bit);
  end component;
  component mult_2
    port(s1, s0, r1, r0 : in  bit;
         t3, t2, t1, t0 : out bit);
  end component;
  component dd
    port (x1, x2, x3, x4, x5, x6 : in  bit;
          y1, y2, y3             : out bit);
  end component;
  component YY
    port(a2, a1, b2, b1, x       : in  bit;
          f6, f5, f4, f3, f2, f1 : out bit);
  end component;
  signal f1, f2, f3, f4, f5, f6, t4, t3, t2, t1, c2, s2, s1 : bit;
begin
  circ1 : YY
    port map (a2, a1, b2, b1, x, f6, f5, f4, f3, f2, f1);
  circ2 : mult_2
    port map (f2, f1, b2, b1, d4, t3, t2, t1);
  circ3 : adder_2
    port map (f4, f3, f6, f5, c2, s2, s1);
  circ4 : dd
    port map (s1, t1, s2, t2, c2, t3, d1, d2, d3);
 
end structure;
 
entity dd is
  port (x1, x2, x3, x4, x5, x6 : in  bit;
        y1, y2, y3             : out bit);
end dd;
architecture struct_1 of dd is
begin
  y1 <= x1 or x2;
  y2 <= x3 or x4;
  y3 <= x5 or x6;
end struct_1;
 
entity YY is
  port (a2, a1, b2, b1, x      : in  bit;
        f6, f5, f4, f3, f2, f1 : out bit);
end YY;
architecture struct_1 of YY is
begin
  f1 <= x and a1;
  f2 <= x and a2;
  f3 <= not x and a1;
  f4 <= not x and a2;
  f5 <= not x and b1;
  f6 <= not x and b2;
end struct_1;

entity VLSI_1 is
  port (a2, a1, b2, b1, x : in  bit;
        d4, d3, d2, d1    : out bit);
end VLSI_1;
 
architecture str of vlsi_1 is
 
  component
    adder_2
    port (a1, b1, a2, b2 : in  bit;
          c2, s2, s1     : out bit);
  end component;
  component mult_2
    port(s1, s0, r1, r0 : in  bit;
         t3, t2, t1, t0 : out bit);
  end component;
  component YY_MUX
    port (t4, t3, t2, t1, c2, s2, s1, x : in  bit;
          d4, d3, d2, d1                : out bit);
  end component;
 
  signal t4, t3, t2, t1, c2, s2, s1 : bit;
 
begin
  circ1 : YY_MUX port map (t4, t3, t2, t1, c2, s2, s1, x,
                          d4, d3, d2, d1); 
  circ2 : mult_2
    port map (a1, b1, a2, b2, t4, t3, t2, t1);
  circ3 : adder_2
    port map (a1, b1, a2, b2, c2, s2, s1);
end str;

entity YY_MUX is
  port (t4, t3, t2, t1, c2, s2, s1, x : in  bit;
        d4, d3, d2, d1                : out bit);
end YY_MUX;
architecture beh of YY_MUX is
begin
  d1 <= (not x and s1) or (x and t1);
  d2 <= (not x and s2) or (x and t2);
  d3 <= (not x and c2) or (x and t3);
  d4 <= x and t4;
end beh;

наверх


наверх
Глава 4. Синтез схем по описаниям на языке VHDL
4.5.1. Кодирование данных типа bit, bit_vector

 
-- синтезированная схема
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity cod_bit is
  port (
    x1 : in  std_logic;
    x2 : in  std_logic;
    x3 : in  std_logic_vector (0 to 3);
    x4 : in  std_logic_vector (7 downto 4);
    y1 : out std_logic;
    y2 : out std_logic_vector (0 to 3)) ;
end cod_bit;
 
architecture examp of cod_bit is
begin
  p0 : NO2 port map (Y => y2(3), A => x4(6), B => x3(1));
  p1 : NA2 port map (Y => y2(2), A => x3(0), B => x4(7));
  p2 : EX2 port map (Y => y2(1), A => x4(4), B => x2);
  p3 : O2 port map (Y  => y2(0), A => x3(2), B => x4(5));
  p4 : A2 port map (Y  => y1, A => x2, B => x1);
end examp;

entity cod_bit is
  port(
    x1, x2 : in  bit;
    x3     : in  bit_vector (0 to 3);
    x4     : in  bit_vector (7 downto 4);
    y1     : out bit;
    y2     : out bit_vector (0 to 3));
end cod_bit;
 
architecture examp of cod_bit is
begin
  y1    <= x1 and x2;
  y2(0) <= x3(2) or x4(5);
  y2(1) <= x4(4) xor x2;
  y2(2) <= x3(0) nand x4(7);
  y2(3) <= x3(1) nor x4(6);
end examp;

наверх

4.5.2. Кодирование данных типа std_logic, std_logic_vector

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity cod_std is
  port(
    x1, x2 : in  std_logic;
    x3     : in  std_logic_vector (0 to 3);
    x4     : in  std_logic_vector (7 downto 4);
    y1     : out std_logic;
    y2     : out std_logic_vector (0 to 3));
end cod_std;
 
architecture examp of cod_std is
begin
  y1    <= x1 and x2;
  y2(0) <= x3(2) or x4(5);
  y2(1) <= x4(4) xor x2;
  y2(2) <= x3(0) nand x4(7);
  y2(3) <= x3(1) nor x4(6);
end examp;

наверх

4.5.3. Кодирование данных типа std_ulogic, std_ulogic_vector

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity cod_u_std is
  port(
    x1, x2 : in  std_ulogic;
    x3     : in  std_ulogic_vector (0 to 3);
    x4     : in  std_ulogic_vector (7 downto 4);
    y1     : out std_ulogic;
    y2     : out std_ulogic_vector (0 to 3));
end cod_u_std;
 
architecture examp of cod_u_std is
begin
  y1    <= x1 and x2;
  y2(0) <= x3(2) or x4(5);
  y2(1) <= x4(4) xor x2;
  y2(2) <= x3(0) nand x4(7);
  y2(3) <= x3(1) nor x4(6);
end examp;

наверх

4.5.4. Кодирование данных типа integer

entity my_int_32 is
  port(
    x1, x2 : in  integer;
    y      : out integer);
end my_int_32;
 
architecture str of my_int_32 is
begin
  y <= x1 + x2;
end str;

package pack is
-- type my_int1 is range 2 to 4;
  type my_int1 is range 4 downto 2;
end pack;
 
package body pack is
end pack;
 
use work.pack.all;
entity my_int is
  port(
    x1, x2 : in  my_int1;
    y      : out my_int1);
end my_int;
 
architecture str of my_int is
begin
  y <= x1 + x2;
end str;

наверх

4.5.5.Кодирование данных перечислимого типа

library exemplar;
use exemplar.exemplar_1164.all;
 
package pack is
  type exemplar_string_array is array
    (natural range <>, natural range <>) of character;
  attribute TYPE_ENCODING             : exemplar_string_array;
  type my_state is (state1, state2, state3);
  attribute TYPE_ENCODING of my_state : type is ("11", "01", "10");
end pack;

library exemplar;
use exemplar.exemplar_1164.all;
use work.pack.all;
entity state is
  port(
    x1, x2 : in  integer range 0 to 3;
    y      : out my_state);
end state;
 
architecture str of state is
 
begin
  p0 : process (x1, x2)
  begin
    if x1 > x2 then y    <= state1;
    elsif x1 < x2 then y <= state2;
    elsif x1 = x2 then y <= state3;
    end if;
  end process;
end str;
library exemplar;
use exemplar.exemplar_1164.all;
 
package pack is
  type my_state is (state1, state2, state3);
  attribute TYPE_ENCODING_STYLE of my_state :
    type is ONEHOT;
 
--  attribute TYPE_ENCODING_STYLE of my_state : 
--  type is BINARY;
 
--  attribute TYPE_ENCODING_STYLE of my_state :
--  type is GRAY;
 
--  attribute TYPE_ENCODING_STYLE of my_state :
--  type is RANDOM;
end pack;
 
package body pack is
end pack;

наверх

4.5.6. Кодирование данных типа array

library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- интерфейс схемы massiv
entity massiv is
  port (
    aa_1_1 : in  std_logic;
    aa_1_0 : in  std_logic;
    aa_2_1 : in  std_logic;
    aa_2_0 : in  std_logic;
    aa_3_1 : in  std_logic;
    aa_3_0 : in  std_logic;
    bb_1_1 : in  std_logic;
    bb_1_0 : in  std_logic;
    bb_2_1 : in  std_logic;
    bb_2_0 : in  std_logic;
    bb_3_1 : in  std_logic;
    bb_3_0 : in  std_logic;
    cc_1_2 : out std_logic;
    cc_1_1 : out std_logic;
    cc_1_0 : out std_logic;
    cc_2_2 : out std_logic;
    cc_2_1 : out std_logic;
    cc_2_0 : out std_logic;
    cc_3_2 : out std_logic;
    cc_3_1 : out std_logic;
    cc_3_0 : out std_logic) ;
end massiv;

package vv is
 
  type in_array is array (natural range 1 to 3)
    of integer range 0 to 3;
  type out_array is array (natural range 1 to 3)
    of integer range 0 to 6;
end vv;
 
package body vv is
end vv;
 
library work;
use work.vv.all;
entity massiv is
  port (AA, BB : in  in_array;
        CC     : out out_array);
end massiv;
 
architecture functional
  of massiv is
begin
  p0 : process (AA, BB)
    variable DD : out_array;
  begin
    loop1 : for i in 1 to 3 loop
      DD(i) := AA(i) + BB(i);
    end loop loop1;
    CC <= DD;
  end process;
end functional;

наверх

4.5.7.Кодирование данных типа character

-- Интерфейс синтезированной схемы my_character. 
 
entity my_character is
  port (
    x1 : in  std_logic;
    x2 : in  std_logic;
    y  : out std_logic_vector (7 downto 0)) ;
end my_character;

entity my_character is
  port(x1, x2 : in  bit;
       y      : out character);
end my_character;
architecture str of my_character is
begin
  p0 : process (x1, x2)
  begin
    if x1 = x2 then y     <= 'A';
    elsif x1 /= x2 then y <= 'B';
    end if;
  end process;
end str;

-- Тест для моделирования синтезированной схемы my_character
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test_char is
end test_char;
architecture str of test_char is
  component my_character
    port (
      x1 : in  std_logic;
      x2 : in  std_logic;
      y  : out std_logic_vector (7 downto 0)) ;
  end component;
  signal x1 : std_logic;
  signal x2 : std_logic;
  signal y  : std_logic_vector (7 downto 0);
begin
  p0 : my_character port map (x1, x2, y);
  x1 <= '0', '1' after 100 ns, '1' after 200 ns;
  x2 <= '1', '1' after 100 ns, '0' after 200 ns;
end str;

наверх

4.5.8. Кодирование строковых литералов

--  Интерфейс синтезированной схемы string_lit 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity string_lit is
  port (
    x1    : in  std_logic;
    x2    : in  std_logic;
    y_3_7 : out std_logic;
    y_3_6 : out std_logic;
    y_3_5 : out std_logic;
    y_3_4 : out std_logic;
    y_3_3 : out std_logic;
    y_3_2 : out std_logic;
    y_3_1 : out std_logic;
    y_3_0 : out std_logic;
    y_2_7 : out std_logic;
    y_2_6 : out std_logic;
    y_2_5 : out std_logic;
    y_2_4 : out std_logic;
    y_2_3 : out std_logic;
    y_2_2 : out std_logic;
    y_2_1 : out std_logic;
    y_2_0 : out std_logic;
    y_1_7 : out std_logic;
    y_1_6 : out std_logic;
    y_1_5 : out std_logic;
    y_1_4 : out std_logic;
    y_1_3 : out std_logic;
    y_1_2 : out std_logic;
    y_1_1 : out std_logic;
    y_1_0 : out std_logic) ;
end string_lit;

entity string_lit is
  port(
    x1, x2 : in  bit;
    y      : out string (3 downto 1));
end string_lit;
 
architecture str of string_lit is
begin
  p0 : process (x1, x2)
  begin
    if x1 = x2 then y     <= "cdA";
    elsif x1 /= x2 then y <= "&h+";
    end if;
  end process;
end str;

наверх

4.5.9. Кодирование данных типа record

package pack is
  type my_record is
  record
    my_bit   : bit;
    my_chart : character;
    my_int   : integer range 0 to 3;
  end record;
 
  type your_record is
  record
    your_bit   : bit;
    your_chart : character;
    your_int   : integer range 0 to 3;
  end record;
end pack;
 
package body pack is
end pack;

--  Интерфейс синтезированной схемы test_rec 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity test_rec is
  port (
    a_my_bit       : in  std_logic;
    a_my_chart_7   : in  std_logic;
    a_my_chart_6   : in  std_logic;
    a_my_chart_5   : in  std_logic;
    a_my_chart_4   : in  std_logic;
    a_my_chart_3   : in  std_logic;
    a_my_chart_2   : in  std_logic;
    a_my_chart_1   : in  std_logic;
    a_my_chart_0   : in  std_logic;
    a_my_int_1     : in  std_logic;
    a_my_int_0     : in  std_logic;
    b_your_bit     : out std_logic;
    b_your_chart_7 : out std_logic;
    b_your_chart_6 : out std_logic;
    b_your_chart_5 : out std_logic;
    b_your_chart_4 : out std_logic;
    b_your_chart_3 : out std_logic;
    b_your_chart_2 : out std_logic;
    b_your_chart_1 : out std_logic;
    b_your_chart_0 : out std_logic;
    b_your_int_1   : out std_logic;
    b_your_int_0   : out std_logic) ;
end test_rec;

library work; use work.pack.all;
               entity test_rec is
                 port(
                   A : in  my_record;
                   B : out your_record);
               end test_rec;
               architecture str of test_rec is
               begin
                 p0 : process (A)
                 begin
                   if A.my_bit = '0' then B.your_bit     <= '1';
                   elsif A.my_bit /= '0' then B.your_int <= 1;
--  B.your_bit <= '0';
                   end if;
                 end process;
               end str;

--  Тест для моделирования схемы test_rec
 
use work.pack.all;
entity test is
end test;
architecture str of test is
  component test_rec
    port(
      A : in  my_record;
      B : out your_record);
  end component;
  signal A : my_record;
  signal B : your_record;
 
begin
  p0 : test_rec port map (A, B);
 
  A.my_bit   <= '0', '1' after 100 ns;
  A.my_chart <= 'A', 'c' after 100 ns;
  A.my_int   <= 3, 2     after 100 ns;
 
end str;

наверх

4.6.1.Использование констант в логических выражениях

entity const_log is
  port(
    x1, x2 : in  bit_vector (0 to 4);
    y      : out bit_vector (0 to 4));
end const_log;
architecture beh of const_log is
  constant b : bit_vector (0 to 4) := "01010";
begin
  y <= (x1 and x2) or b;                -- поразрядные логические
-- операции and, or
end beh;

наверх

4.6.2. Использование переменных в логических выражениях

entity var0 is
  port(
    x1, x2, x3, x4 : in  bit;
    y              : out bit);
end var0;
 
architecture str of var0 is
begin
  p0 : process (x1, x2, x3, x4)
    variable a, b, c, d : bit;
  begin
 
    a :=(x1 and not x2);
    c :=a;
    b :=(not x1 and x2);
    d :=b;
    y <=c or b;
 
  end process p0;
end str;

entity var is
  port(x1, x2, x3, x4 : in  bit;
       y              : out bit);
end var;
architecture str of var is
begin
  p0 : process (x1, x2, x3, x4)
    variable a, b, c, d : bit;
  begin
    a :=(x1 and not x2);
    b :=(not x1 and x2);
    c :=a or b;
    a :=(x3 and not x4);
    b :=(not x3 and x4);
    d :=a or b;
    y <= c or d;
  end process p0;
end str;

наверх

4.6.3. Общие переменные

--  Не синтезируемый VHDL-код
 
entity example_1_shared is
  port(
    x1     : in  integer;
    y1, y2 : out integer);
end example_1_shared;
 
architecture beh of example_1_shared is
  shared variable COUNT : integer;
begin
  p1 : process (x1)
  begin
    Count := 1;
    y1    <= x1 + COUNT;
  end process;
 
  p2 : process (x1)
  begin
    Count := 3;
    y2    <= x1 + COUNT;
  end process;
end beh;

entity example_2_shared is
  port(
    x1     : in  integer range 0 to 3;
    y1, y2 : out integer range 0 to 6);
end example_2_shared;
 
architecture beh of example_2_shared is
  shared variable COUNT : integer := 1;
begin
  p1 : process (x1)
  begin
    y1 <= x1 + COUNT;
  end process;
  p2 : process (x1)
  begin
    y2 <= x1 + COUNT;
  end process;
end beh;

наверх

4.6.4. Логические операторы над типом std_logic

--   Синтезированный VHDL-код схемы example_std
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package components is
  component VCC
    port (
      Y : out std_logic) ;
  end component;
  component GND
    port (
      Y : out std_logic) ;
  end component;
end components;
 
package body components is
end components;
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity example_std is
  port (
    x1 : in  std_logic_vector (4 downto 0);
    x2 : in  std_logic_vector (4 downto 0);
    y1 : out std_logic_vector (4 downto 0)) ;
end example_std;
architecture str of example_std is
  signal y1_0_EXMPLR, y1_1_EXMPLR : std_logic;
begin
  y1(4) <= y1_0_EXMPLR;
  y1(3) <= y1_1_EXMPLR;
  y1(1) <= y1_1_EXMPLR;
  y1(0) <= y1_0_EXMPLR;
  y1(2) <= y1_0_EXMPLR when y1_0_EXMPLR = '1' else 'Z';
  p1 : work.components.VCC port map (Y => y1_1_EXMPLR);
  p2 : work.components.GND port map (Y => y1_0_EXMPLR);
end str;

 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity example_std is
  port(x1, x2 : in  std_logic_vector (4 downto 0);
         y1   : out std_logic_vector (4 downto 0)) ;
end example_std;
architecture str of example_std is
  constant w1 : std_logic_vector := ('U', '1', 'U', 'X', 'X');
  constant w2 : std_logic_vector := ('L', 'H', 'Z', 'H', 'W');
begin
  y1 <= w1 and w2;
end str;

library IEEE;
use IEEE.std_logic_1164.all;
entity GND is
  port(Y : out std_logic);
end;
architecture GND_arch of GND is
begin
  Y <= '0';
end GND_arch;

library IEEE;
use IEEE.std_logic_1164.all;
entity VCC is
  port(Y : out std_logic);
end;
architecture VCC_arch of VCC is
begin
  Y <= '1';
end VCC_arch;

наверх

4.6.5. Арифметические операторы

entity arithm_1 is
  port(
    x1, x2 : in  integer range 0 to 4;
    y      : out integer range -4 to 4);
end arithm_1;
 
architecture beh of arithm_1 is
begin
  y <= x1 - x2;
end beh;

--  Тест для моделирования синтезированной схемы arithm_1
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test is
end test;
architecture beh of test is
  component arithm_1
    port (
      x1 : in  std_logic_vector (2 downto 0);
      x2 : in  std_logic_vector (2 downto 0);
      y  : out std_logic_vector (3 downto 0)) ;
  end component;
  signal x1 : std_logic_vector (2 downto 0);
  signal x2 : std_logic_vector (2 downto 0);
  signal y  : std_logic_vector (3 downto 0);
begin
 
  p0 : arithm_1 port map (x1, x2, y);
 
  x2 <= "111" after 50 ns
        , "110" after 100 ns
        , "101" after 150 ns
        , "100" after 200 ns
        , "011" after 250 ns
        , "000" after 300 ns;
  x1 <= "010" after 50 ns;
end beh;

package pack is
  type my_int1 is range 2 to 4;         -- положительные числа 
-- type my_int1 is range -4 to -2;
-- отрицательные числа
end pack;
 
package body pack is
end pack;
 
use work.pack.all;
entity type_my_int is
  port(
    x1, x2 : in  my_int1;
    y      : out my_int1);
end type_my_int;
 
architecture str of type_my_int is
begin
  y <= x1 + x2;
end str;

наверх

4.6.6. Оператор if

--  Синтезированный VHDL-код
 
procedure DFFPC (
  constant data   : in  std_logic;
  constant preset : in  std_logic;
  constant clear  : in  std_logic;
  signal clk      : in  std_logic;
  signal q        : out std_logic)
is begin
     if (preset = '1') then
       q <= '1';
     elsif (clear = '1') then
       q <= '0';
     elsif (clk'event and clk'last_value = '0' and clk = '1') then
       q <= data and data;              -- takes care of q<='X' if data='Z'
     end if;
     if ((clear /= '1' or preset /= '1') and clk /= '0' and clk /= '1')
     then q <= 'X';
     end if;
   end DFFPC;

entity example0_if is
  port(
    x1, x2, contr : in  boolean;
    y             : out boolean);
end example0_if;
architecture beh of example0_if is
begin
  process (x1, x2, contr)
    variable n : boolean;
  begin
    if contr then n := x1;
    else n          := x2;
    end if;
    y               <= n;
  end process;
end beh;

entity example2_if is
  port(
    x1, x2 : in  bit;
    y      : out bit);
end example2_if;
 
architecture beh of example2_if is
begin
  process (x1, x2)
 
  begin
    if x1 = x2 then y     <= '1';
    elsif x1 /= x2 then y <= '0';
    end if;
  end process;
end beh;

entity example3_if is
  port(
    x1, x2 : in  integer range 0 to 2;
    y      : out integer range 1 to 3);
end example3_if;
 
architecture beh of example3_if is
begin
  process (x1, x2)
  begin
    if x1 = x2 then y     <= 1;
    elsif x1 >= x2 then y <= 2;
    else y                <= 3;
    end if;
  end process;
end beh;

наверх

4.6.7.Использование констант в арифметических выражениях

entity const is
  port(
    x1 : in  integer range 0 to 3;
    y  : out integer range 0 to 10);
end const;
 
architecture beh of const is
  constant a : integer := 5;
begin
  y <= x1 + a;
end beh;

наверх

4.6.8. Оператор case

entity control_case is
  port (sel : in bit_vector (0 to 1); a, b, c, d : in bit; m : out bit);
end control_case;
architecture example of control_case is
begin
  process (sel, a, b, c, d)
  begin
    case sel is
      when "00"   => m <= a;
      when "01"   => m <= b;
      when "10"   => m <= c;
      when others => m <= d;
    end case;
  end process;
end example;

наверх

4.6.9. Оператор цикла

entity control_loop is
  port (a :     bit_vector (0 to 3);
        m : out bit_vector (0 to 3)); 
end control_loop;
 
architecture example of control_loop is
begin
  process (a)
    variable b : bit;
  begin
    b := '1';
    for i in 0 to 3 loop
      b    := a(3-i) and b;
      m(i) <= b;
    end loop;
  end process;
end example;

--  Не синтезируемый VHDL-код
 
entity while_loop is
  port (inp_sig : in  bit_vector (3 downto 0);
        ena     : in  bit;
        result  : out bit_vector (3 downto 0));
end while_loop;
 
architecture example of while_loop is
begin
  process (inp_sig)
    variable i : integer := 0;          --  ошибка инициализации 
  begin
    while (i < 2) loop
      result (i) <= ena and inp_sig(i);
      i          := i + 1;
    end loop;
  end process;
end example;

entity while_loop is
  port (inp_sig : in  bit_vector (3 downto 0);
        ena     : in  bit;
        result  : out bit_vector (3 downto 0));
end while_loop;
 
architecture example of while_loop is
begin
  process (inp_sig)
    variable i : integer;
  begin
 
    i := 0;
    while (i < 4) loop
      result (i) <= ena and inp_sig(i);
      i          := i + 1;
    end loop;
  end process;
end example;

наверх

4.6.10.Выходной порт нельзя использовать в выражениях

--  Не синтезируемый VHDL-код
 
entity out_port is
  port(
    x1, x2, x3 : in  bit;
    y1, y2     : out bit);
end out_port;
architecture beh of out_port is
begin
  y1 <= (x1 and x2);
  y2 <= (x1 xor x3) or y1;              -- ошибка, y1 выходной порт
end beh;

entity out_port is
  port(
    x1, x2, x3 : in  bit;
    y1, y2     : out bit);
end out_port;
 
architecture beh of out_port is
  signal z : bit;                       -- дополнительный внутренний сигнал
begin
 
  z  <= (x1 and x2);
  y1 <= z;
  y2 <= (x1 xor x3) or z;
 
end beh;

наверх

4.6.11. Оператор assert

package vv is
 
  type in_array is array (natural range 1 to 3)
    of integer range 0 to 3;
  type out_array is array (natural range 1 to 3)
    of integer range 0 to 6;
end vv;
 
package body vv is
end vv;
 
library work;
use work.vv.all;
entity massiv is
  port (AA, BB : in  in_array;
        CC     : out out_array);
end massiv;
 
architecture func_ass
  of massiv is
begin
  p0 : process (AA, BB)
    variable DD : out_array;
  begin
 
    assert (AA'length = BB'length)
      report "Size AA =/ Size BB" severity error;  -- оператор сообщения игнорируется
    -- при синтезе
    loop1 : for i in 1 to 3 loop
      DD(i) := AA(i) + BB(i);
    end loop loop1;
    CC <= DD;
  end process;
end func_ass;

наверх

4.6.12. Оператор wait

Не синтезируемый VHDL-код.
 
  library IEEE;
use IEEE.std_logic_1164.all;
 
entity wait_pro is
  port(
    x1, x2, x3, x4 : in  std_logic;
    y, w, v        : out std_logic);
end wait_pro;
 
architecture beh of wait_pro is
begin
  p0 : process
  begin
    wait until x3 = '1';
    y <= x1 or x2;
    wait until x3 = '1';
    v <= x1 and x2;
    wait until x4 = '1';                -- условия ожидания должны
    --   быть одинаковыми
    w <= x1 xor x2;
  end process;
end beh;

наверх

4.6.13. Операторы сдвига

library IEEE;
use IEEE.STD_LOGIC_1164. all;
use IEEE.NUMERIC_STD. all;
entity shift_example is
  port (a, b   : in  std_logic_vector (3 downto 0);
        x1, x2 : out std_logic_vector (3 downto 0)); 
end shift_example;
 
architecture Synt of shift_example is
  signal y, z : std_logic_vector (3 downto 0);
begin
 
  y <= std_logic_vector(unsigned'(shift_left
                                    (unsigned(a), 3)));
  z <= std_logic_vector(unsigned'(shift_right
                                  (unsigned(a), 3))); 
  x1 <= y and b;
  x2 <= z xor b;
 
end Synt;

library IEEE;
use IEEE.STD_LOGIC_1164. all;
library exemplar;
use exemplar.exemplar_1164.all;
entity shift_example is
  port (a, b   : in  std_logic_vector (3 downto 0);
        x1, x2 : out std_logic_vector (3 downto 0)); 
end shift_example;
architecture Synt of shift_example is
  signal y, z : std_logic_vector (3 downto 0);
begin
  y  <= sl (a, 3);                      -- сдвиг влево
  z  <= sr (a, 3);                      -- сдвиг вправо 
  x1 <= y and b;
  x2 <= z xor b;
end Synt;

наверх

4.6.14. Оператор generate

--  Интерфейс синтезированной схемы multic_1
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity multic_1 is
  port (
    aa_1_1_1 : in  std_logic;
    aa_1_1_0 : in  std_logic;
    aa_1_2_1 : in  std_logic;
    aa_1_2_0 : in  std_logic;
    aa_1_3_1 : in  std_logic;
    aa_1_3_0 : in  std_logic;
    aa_2_1_1 : in  std_logic;
    aa_2_1_0 : in  std_logic;
    aa_2_2_1 : in  std_logic;
    aa_2_2_0 : in  std_logic;
    aa_2_3_1 : in  std_logic;
    aa_2_3_0 : in  std_logic;
    aa_3_1_1 : in  std_logic;
    aa_3_1_0 : in  std_logic;
    aa_3_2_1 : in  std_logic;
    aa_3_2_0 : in  std_logic;
    aa_3_3_1 : in  std_logic;
    aa_3_3_0 : in  std_logic;
    bb_1_1_1 : in  std_logic;
    bb_1_1_0 : in  std_logic;
    bb_1_2_1 : in  std_logic;
    bb_1_2_0 : in  std_logic;
    bb_1_3_1 : in  std_logic;
    bb_1_3_0 : in  std_logic;
    bb_2_1_1 : in  std_logic;
    bb_2_1_0 : in  std_logic;
    bb_2_2_1 : in  std_logic;
    bb_2_2_0 : in  std_logic;
    bb_2_3_1 : in  std_logic;
    bb_2_3_0 : in  std_logic;
    bb_3_1_1 : in  std_logic;
    bb_3_1_0 : in  std_logic;
    bb_3_2_1 : in  std_logic;
    bb_3_2_0 : in  std_logic;
    bb_3_3_1 : in  std_logic;
    bb_3_3_0 : in  std_logic;
    cc_1_1_5 : out std_logic;           -- лишний выходной полюс
    cc_1_1_4 : out std_logic;
    cc_1_1_3 : out std_logic;
    cc_1_1_2 : out std_logic;
    cc_1_1_1 : out std_logic;
    cc_1_1_0 : out std_logic;
    cc_1_2_5 : out std_logic;           -- лишний выходной полюс
    cc_1_2_4 : out std_logic;
    cc_1_2_3 : out std_logic;
    cc_1_2_2 : out std_logic;
    cc_1_2_1 : out std_logic;
    cc_1_2_0 : out std_logic;
    cc_1_3_5 : out std_logic;           -- лишний выходной полюс
    cc_1_3_4 : out std_logic;
    cc_1_3_3 : out std_logic;
    cc_1_3_2 : out std_logic;
    cc_1_3_1 : out std_logic;
    cc_1_3_0 : out std_logic;
    cc_2_1_5 : out std_logic;           -- лишний выходной полюс
    cc_2_1_4 : out std_logic;
    cc_2_1_3 : out std_logic;
    cc_2_1_2 : out std_logic;
    cc_2_1_1 : out std_logic;
    cc_2_1_0 : out std_logic;
    cc_2_2_5 : out std_logic;           -- лишний выходной полюс
    cc_2_2_4 : out std_logic;
    cc_2_2_3 : out std_logic;
    cc_2_2_2 : out std_logic;
    cc_2_2_1 : out std_logic;
    cc_2_2_0 : out std_logic;
    cc_2_3_5 : out std_logic;           -- лишний выходной полюс
    cc_2_3_4 : out std_logic;
    cc_2_3_3 : out std_logic;
    cc_2_3_2 : out std_logic;
    cc_2_3_1 : out std_logic;
    cc_2_3_0 : out std_logic;
    cc_3_1_5 : out std_logic;           -- лишний выходной полюс
    cc_3_1_4 : out std_logic;
    cc_3_1_3 : out std_logic;
    cc_3_1_2 : out std_logic;
    cc_3_1_1 : out std_logic;
    cc_3_1_0 : out std_logic;
    cc_3_2_5 : out std_logic;           -- лишний выходной полюс
    cc_3_2_4 : out std_logic;
    cc_3_2_3 : out std_logic;
    cc_3_2_2 : out std_logic;
    cc_3_2_1 : out std_logic;
    cc_3_2_0 : out std_logic;
    cc_3_3_5 : out std_logic;           -- лишний выходной полюс
    cc_3_3_4 : out std_logic;
    cc_3_3_3 : out std_logic;
    cc_3_3_2 : out std_logic;
    cc_3_3_1 : out std_logic;
    cc_3_3_0 : out std_logic) ;
end multic_1;

library work;
use work.vvvv.all;
entity multic_1 is
  port (AA, BB : in  in_array;
        CC     : out out_array);
end multic_1;
 
architecture functional
  of multic_1 is
  component
    element
    port (x1, y1, x2, y2, x3, y3 : in  integer;
          w                      : out integer);
  end component;
 
begin
  q_i : for i in 1 to 3 generate
    q_j : for j in 1 to 3 generate
      el_ij : element
        port map (x1 => AA(i, 1), y1 => BB(1, j),
                  x2 => AA(i, 2), y2 => BB(2, j),
                  x3 => AA(i, 3), y3 => BB(3, j),
                  w  => CC(i, j));              
    end generate;
  end generate;
end functional;
 
entity element is
  port(x1, y1, x2, y2, x3, y3 :
       in integer range 0 to 3;
       w : out integer range 0 to 32);
end element;
 
architecture functional of element is
begin
  w <= ((x1*y1)+ (x2 * y2)+ (x3 * y3));
end functional;
 
package vvvv is
  type in_array is array (natural range 1 to 3,
                          natural range 1 to 3)
    of integer range 0 to 3;
  type out_array is array (natural range 1 to 3,
                           natural range 1 to 3)
    of integer range 0 to 32;
end vvvv;
 
package body vvvv is
end vvvv;

-- Тест для моделирования схемы multic_1
 
library work;
use work.vv_vls.all;
entity test_multic_1 is
end test_multic_1;
 
architecture struct
  of test_multic_1 is
  component
    multic_1
    port (AA, BB : in  in_array;
          CC     : out out_array);
  end component;
  signal AA, BB : in_array;
  signal CC     : out_array;
begin
  p1 : multic_1 port map (AA, BB, CC);
 
  AA <= ((1, 3, 1),
         (2, 3, 1),
         (2, 3, 1));
 
  BB <= ((2, 2, 1),
          (2, 3, 1),
          (1, 3, 1));
end struct;

наверх

4.6.15. Использование изменяемых параметров (generic)

entity gen_circ is
  port (a1, a2, b1, b2, b3 : in  bit;
        w                  : in  bit;
        f                  : out bit);
end gen_circ;
 
architecture str of gen_circ is
 
  component or_2
    port (x1, x2 : in  bit;
          y      : out bit);
  end component;
 
  component mp_vour
    generic (N : natural := 4);
    port (x  : in  bit_vector (0 to 2*N);
          u8 : out bit);
  end component;
 
  signal z  : bit;
  signal ss : bit_vector (0 to 4);
begin
  ss <= (a1, a2, b1, b2, b3);
  p0 : mp_vour
    generic map (N => 2)                -- ключевое соответствие
--  generic map (2)      -- позиционное соответствие 
    port map (ss, z);
  p1 : or_2 port map (z, w, f);
end str;
 
entity or_2 is
  port (x1, x2 : in  bit;
        y      : out bit);
end or_2;
 
architecture struct of or_2 is
begin
  y <= x1 or x2;
end struct;

entity mp_vour is
  generic (N : natural := 4);
  port (x  : in  bit_vector (0 to 2*N);
        u8 : out bit);
end mp_vour;
architecture gomain of mp_vour is
  component xor2
    port (x1, x2 : in  bit;
          y      : out bit);
  end component;
  component nand2
    port (x1, x2 : in  bit;
          y      : out bit);
  end component;
  signal ss : bit_vector (0 to 2*N);
begin
  ss(0) <= x(0);
  g4 : for i in 1 to N generate
    gn : nand2 port map (x1 => ss(2*(i-1)), x2 => x(2*i-1), y => ss(2*i-1));
    gx : xor2 port map (x1  => ss(2*i-1), x2 => x(2*i), y => ss(2*i));
  end generate g4;
  u8 <= ss (2*N);
end gomain;
 
entity nand2 is
  port (x1, x2 : in  bit;
        y      : out bit);
end nand2;
architecture struct of nand2 is
begin
  y <= x1 nand x2;
end struct;
 
entity xor2 is
  port (x1, x2 : in  bit;
        y      : out bit);
end xor2;
architecture struct of xor2 is
begin
  y <= x1 xor x2;
end struct;

--  Тест для моделирования схемы gen_circ
 
entity test_gen_circ is
end test_gen_circ;
 
architecture struct
  of test_gen_circ is
 
  component
    gen_circ
    port (rr : in  bit_vector (0 to 4);
          w  : in  bit;
          f  : out bit);
  end component;
  signal rr : bit_vector (0 to 4);
  signal w  : bit;
  signal f  : bit;
begin
 
  p1 : gen_circ port map (rr, w, f);
 
  rr <= "01010", "00000" after 50 ns, "11111" after 100ns;
  w  <= '0', '1'         after 50 ns, '1' after 100ns;
end struct;

наверх

4.6.16. Оператор конкретизации компонента

entity add1 is
  port (b1, b2 : in  bit;
        c1, s1 : out bit);
end add1;
 
architecture struct_1 of add1 is
begin
  s1 <= ((b1 and (not b2)) or ((not b1) and b2));
  c1 <= b1 and b2;
end struct_1;
 
architecture struct_2 of add1 is
begin
  s1 <= b1 xor b2;
  c1 <= b1 and b2;
end struct_2;

entity add2 is
  port (c1, a1, a2 : in  bit;
        c2, s2     : out bit);
end add2;
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and a1 and (not a2)) or
        (c1 and (not a1)and (not a2)) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

entity adder_2_mod is
  port (x1, y1, x2, y2 : in  bit;
        c2, s2, s1     : out bit);
end adder_2_mod;
architecture struct_1 of adder_2_mod is
  component add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
  component add2
    port(c1, a1, a2 : in  bit;
         c2, s2     : out bit);
  end component;
  signal c1 : bit;                      -- раздел деклараций внутренних
-- сигналов схемы adder_2
begin
  circ1 : add1
    port map (b1 => y1, b2 => y2, c1 => c1, s1 => s1);
  circ2 : add2
    port map (c1 => c1, a1 => '0', a2 => '0', c2 => c2, s2 => s2);
end struct_1;

наверх

4.6.18. Начальное значение порта игнорируется

entity adder_2 is
  port (a1         : in  bit := '0';    -- начальное значение
        -- игнорируется
        b1, a2, b2 : in  bit;
        s1         : out bit := '1';    -- начальное значение
        -- игнорируется
        c2, s2     : out bit);
end adder_2;

наверх

4.6.19. Использование глобальных сигналов

entity add1 is
  port (b1, b2 : in  bit;
        c1, s1 : out bit);
end add1;
 
architecture struct_1 of add1 is
begin
  s1 <= ((b1 and (not b2)) or ((not b1) and b2));
  c1 <= b1 and b2;
end struct_1;
 
architecture struct_2 of add1 is
begin
  s1 <= b1 xor b2;
  c1 <= b1 and b2;
end struct_2;

entity add2 is
  port (c1, a1, a2 : in  bit;
        c2, s2     : out bit);
end add2;
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and a1 and (not a2)) or
        (c1 and (not a1)and (not a2)) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

--   Не синтезируемый VHDL-код
 
library work;
use work.pack.all;
 
entity adder_2 is
  port (a1, b1, a2, b2 : in  bit;
        c2, s2, s1     : out bit);
end adder_2;
 
architecture struct_1 of adder_2 is
  component
    add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
  component add2
    port(c1, a1, a2 : in  bit;
         c2, s2     : out bit);
  end component;
-- signal c1:BIT := '1'; -- сигнал декларирован в
-- пакете  pack
begin
  circ1 : add1
    port map (b1, b2, c1, s1);
  circ2 : add2
    port map (c1, a1, a2, c2, s2);
end struct_1;
 
package pack is
  signal C1 : bit;                      -- декларация сигнала C1 
end pack;
 
package body pack is
end pack;

наверх

4.6.20. Оператор вызов функции

entity FACTORIAL is
  port (NUM    : in  integer range 1 to 4;
        RESULT : out integer range 1 to 24);
end FACTORIAL;
architecture RTL of FACTORIAL is
  pure function FACT (constant N : in integer range 1 to 4)
    return integer is
  begin
    if (N = 1) then
      return 1;
    elsif (N > 1) and (N < 4) then
      return N * FACT (N - 1);
    -- рекурсивный вызов функции допускается
    else
      return 0;
    end if;
  end FACT;
begin
  RESULT <= FACT (NUM);
end RTL;

наверх

4.6.21. Схемная реализация разрешающей функции

library IEEE;
use IEEE.std_logic_1164.all;
entity A2 is
  port(A, B : in  std_logic;
        Y   : out std_logic);
end;
architecture A2_arch of A2 is
begin
  Y <= A and B;
end A2_arch;

library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.wire.all;
 
entity circuit_wire is
  port(x1, x2, x3, x4, x5, x6 : in  std_logic;
       out_circ               : out std_logic);
end circuit_wire;
 
architecture structure of circuit_wire is
  component A2 is
    port(A, B : in  std_logic;
          Y   : out std_logic);
  end component;
 
  signal out_wire : RESOLVED_BIT;
begin
  p1 : A2
    port map (A => x1, B => x2, Y => out_wire);
  p2 : A2
    port map (a => x3, b => x4, y => out_wire);
  p3 : A2
    port map (A => x5, b => x6, Y => out_wire);
  p4 : A2
    port map (a => out_wire, B => x2, y => out_circ);
end structure;

 
 
library IEEE;
use IEEE.std_logic_1164.all;
package wire is
  function RES_FUNC(DATA : in std_logic_vector) return std_logic;
  subtype RESOLVED_bit is RES_FUNC std_logic;
 
end;
 
package body wire is
  function RES_FUNC(DATA : in std_logic_vector) return std_logic is
  begin
    for I in DATA'range loop
      if DATA(I) = '1' then
        return '1';
      end if;
    end loop;
    return '0';
  end; end;

наверх

4.6.22. Переименования (alias)

entity alia is
  port(
    mass   : in  bit_vector (9 downto 4);
    output : out bit);
end alia;
 
architecture beh of alia is
 
  function left_or (mass : bit_vector) return bit is
    alias aliased_mass : bit_vector (0 to mass'length-1) is mass;
  begin
    return aliased_mass (0) or aliased_mass (1);
  end left_or;
 
begin
  p0 : process (mass)
  begin
    output <= left_or (mass);
  end process;
end beh;

наверх

4.6.23. Схемная реализация атрибутов

entity attr is
  port(
    x_to   : in  bit_vector (0 to 3);
    x_down : in  bit_vector (9 downto 7);
    y1     : out integer range 0 to 7;
    y2     : out integer range 0 to 12;
    y3     : out integer range 0 to 7);
end attr;
 
architecture str of attr is
begin
  y1 <= x_to'left + x_down'right;
  y2 <= x_to'high + x_down'low;
  y3 <= x_to'length + x_down'length;
end str;

library work;
use work.my_PACK.all;
 
entity circuit1 is
  port (y, c, b, x1 : in  bit;
        a           : out bit);
end circuit1;
architecture struct_1 of circuit1 is
  attribute element_log of met1   : label is (1, 1, 1);
  attribute element_log of met2   : label is (2, 2, 2);
  attribute element_log of others : label is (3, 3, 3);
  component nao22
    port (a, b, c, d : in  bit;
          y          : out bit);
  end component;
  component nao2
    port (a, b, c : in  bit;
          y       : out bit);
  end component;
  signal w, d : bit;
begin
  m_3 : nao2
    port map (b => y, y => A, c => d, a => w);
  met1 : nao22
    port map (a => Y, b => C, c => b, D => x1, y => w);
  met2 : NAO22 port map (y, b, c, c, d);
end struct_1;
 
package my_PACK is
  type three_int is record x1, x2, x3 : integer;
  end record;
  attribute element_log               : three_int;
end my_PACK;

entity nao22 is
  port (a, b, c, d : in  bit;
        y          : out bit);
end nao22;
architecture beh_2 of nao22 is
begin
  y <= (not a and not b) or (not c and not d);
end beh_2;

entity nao2 is
  port (a, b, c : in  bit;
        y       : out bit);
end nao2;
architecture beh_1 of nao2 is
begin
  y <= (not a) or (not b and not c);
end beh_1;

наверх

4.6.24. Группы

package GG is
  constant N : integer := 4;
  constant M : integer := 3;
  type my_array is array (natural range 1 to N,
                          natural range 1 to M)
    of integer range 0 to 3;
end GG;
 
package body GG is
end GG;
 
library work;
use work.GG.all;
entity matr_4 is
  port (AA, BB, CC, DD : in  my_array;
        S              : out integer);
end matr_4;
 
architecture functional of matr_4 is
  constant WW                    : integer := M*N;
  group DIMEN_2 is (signal);
  group MATR                     : DIMEN_2 (AA, BB, CC, DD);
  attribute all_elements         : integer;
  attribute all_elements of MATR : group is WW;
 
begin
  S <= MATR'all_elements;
-- VHDL-код может быть более содержательным
end functional;

наверх

4.6.25. Типы сигналов register и bus. Охраняемый блок

-- Не синтезируемый VHDL-код
 
library IEEE;
use IEEE.STD_LOGIC_1164. all;
entity reg is
  port(
    x1, x2, x3, x4 : in  std_logic_vector (0 to 3);
    clk            : in  std_logic;
    z              : out std_logic_vector (0 to 3));
end reg;
architecture beh of reg is
  signal y : std_logic_vector (0 to 3) register;
--  signal y :  std_logic_vector (0 to 3) bus;
begin
  p0 : block (clk = '1')
  begin
    y <= guarded x1 and x2;
    y <= guarded x3 or x4;
    z <= guarded y xor x1;
  end block;
end beh;

--  Тест для моделирования схемы reg
 
library IEEE;
use IEEE.STD_LOGIC_1164. all;
 
entity test_reg is
end test_reg;
architecture beh of test_reg is
  component reg
    port(
      x1, x2, x3, x4 : in  std_logic_vector (0 to 3);
      clk            : in  std_logic;
      z              : out std_logic_vector (0 to 3));
  end component;
  signal x1, x2, x3, x4, z : std_logic_vector (0 to 3);
  signal clk               : std_logic;
begin
  p0 : reg port map (x1, x2, x3, x4, clk, z);
  x1  <= "1101"   after 50 ns, "1101" after 100 ns, "1101" after 200 ns;
  x2  <= "0101"   after 50 ns, "1101" after 100 ns, "0101" after 200 ns;
  x3  <= "0101"   after 50 ns, "1101" after 100 ns, "0101" after 200 ns;
  x4  <= "0001"   after 50 ns, "1000" after 100 ns, "0001" after 200 ns;
  clk <= '1', '0' after 150 ns;
end beh;

наверх

4.6.26. Охраняемые сигналы

--  Синтезированный VHDL-код схемы discon
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package components is
  component EX2
    port (
      Y : out std_logic;
      A : in  std_logic;
      B : in  std_logic) ;
  end component;
  component A2
    port (
      Y : out std_logic;
      A : in  std_logic;
      B : in  std_logic) ;
  end component;
end components;
package body components is
end components;
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity discon is
  port (
    x1  : in  std_logic;
    x2  : in  std_logic;
    clk : in  std_logic;
    z1  : out std_logic;
    z2  : out std_logic) ;
end discon;
 
architecture beh of discon is
  signal sig1, sig2 : std_logic;
begin
  z1 <= sig1 when clk = '1' else 'Z';
  -- трехстабильный элемент с выходом z1
  z2 <= sig2 when clk = '1' else 'Z';
  -- трехстабильный элемент с выходом z2
  p1 : work.components.EX2 port map (Y => sig2, A => x2, B => x1);
  p2 : work.components.A2 port map (Y  => sig1, A => x2, B => x1);
end beh;

library IEEE;
use IEEE.STD_LOGIC_1164. all;
entity discon is
  port(
    x1, x2 : in  std_logic;
    clk    : in  std_logic;
    z1, z2 : out std_logic);
end discon;
architecture beh of discon is
  signal y1     : std_logic bus := '0';
  signal y2     : std_logic bus;
  disconnect y1 : std_logic after 10 ns;
  disconnect y2 : std_logic after 15 ns;
begin
  p0 : block (clk = '1')
  begin
    y1 <= guarded x1 and x2;
    y2 <= guarded x1 xor x2;
  end block;
  z1 <= y1 after 20 ns;
  z2 <= y2 after 25 ns;
end beh;

entity guard is
  port(
    x1, x2, x3, x4, x5, x6 : in  bit;
    v, w                   : out bit);
end guard;
 
architecture str of guard is
begin
  p1 : block ((x5 and x6) = '1')
 
  begin
    v <= guarded (x1 or x2);
    w <= guarded (x3 xor x4);
  end block;
end str;

наверх

4.6.27. Тип real не поддерживается при синтезе

 
--   Не синтезируемый VHDL-код
 
entity exp1_real is
  port(
    b1 : in  real range 2.0 to 3.14;
    -- ошибка (тип real не поддерживается)
    b2 : in  real range -2.0 to 4.77;   -- ошибка 
    b3 : out real range -4.0 to 8.00);  -- ошибка 
end exp1_real;
architecture str1 of exp1_real is
begin
  b3 <= b1 + b2;
end str1;

наверх

4.6.28. Оператор назначения сигнала

library IEEE;
use IEEE.std_logic_1164.all;
 
entity add1 is
  port (b1, b2 : in  std_logic;
        c1, s1 : out std_logic);
end add1;
 
architecture beh_after of add1 is
begin
  s1 <= transport (b1 xor b2) after 100 ns;
  -- наличие слов after, transport
  -- не влияет на результирующую логическую схему
  c1 <= transport (b1 and b2) after 500 ns;
end beh_after;

library IEEE;
use IEEE.std_logic_1164.all;
 
entity add1 is
  port (b1, b2 : in  std_logic;
        c1, s1 : out std_logic);
end add1;
 
architecture beh_NO_after of add1 is
begin
  s1 <= b1 xor b2;                      -- отсутствие слова after не влияет на 
  -- результирующую логическую схему 
  c1 <= b1 and b2;;
end beh_NO_after;

наверх

4.6.29. Перегрузка операторов (overload)

library work;
use work.over.all;
entity complex_overload is
  port (a, b : in  integer range 0 to 3;
        f, g : in  integer range 0 to 15;
        c    : in  bit;
        z    : in  bit_vector (0 to 3);
        e    : out bit);
end complex_overload;
architecture beh of complex_overload is
  signal d : bit;
  signal t : integer range 0 to 15;
  signal v : bit_vector (0 to 3);
begin
 
  v <= (g and f) and z;
  e <= d and v(2);
  t <= (a * b);
  d <= t * c;
end beh;

library work;
use work.over.all;
entity log_overload_example is
  port (a, b : in  integer range 0 to 15;
          y  : out bit_vector (0 to 3));
end log_overload_example;
 
architecture beh of log_overload_example is
 
begin
  y <= a and b;                         -- перегрузка логической операции and
 
end beh;

library work;
use work.over.all;
entity overload_example is
  port (a   : in  integer range 0 to 15;
          x : in  bit;
          y : out bit);
end overload_example;
 
architecture beh of overload_example is
 
begin
  y <= a * x;                           -- перегружаемый оператор *
 
end beh;

package over is
  function int_to_bin4 (signal INPUT : integer) return bit_vector;
  function "*" (signal a : integer range 0 to 15; b : bit) return bit;
  function "and" (
    signal a : integer range 0 to 15;
    signal b : integer range 0 to 15) return bit_vector;
end over;
 
package body over is
 
  function int_to_bin4
    (signal INPUT   : integer)
    return bit_vector is
    variable fout   : bit_vector(0 to 3);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 3 downto 0 loop
      temp_b := temp_a/(2**i);
      temp_a := temp_a rem (2**i);
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_to_bin4;
 
  function "*" (signal a : integer range 0 to 15; b : bit) return bit is
    variable cc : bit_vector (0 to 3);
  begin
    cc := int_to_bin4 (a);
 
    for I in 0 to 3 loop
      if cc(I) = '1' then
        return ('1' and b);
      end if;
    end loop;
    return ('0' and b);
 
  end "*";
  function "and" (signal a : integer range 0 to 15; signal b : integer range 0 to 15)
    return bit_vector is
    variable aa, bb : bit_vector (0 to 3);
  begin
    aa := int_to_bin4 (a);
    bb := int_to_bin4 (b);
    return (aa and bb);
  end "and";
end over;

--  Тест для моделирования синтезированной схемы complex_overload
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test_overload is
end test_overload;
 
architecture beh of test_overload is
  component complex_overload
    port (
      a : in  std_logic_vector (1 downto 0);
      b : in  std_logic_vector (1 downto 0);
      f : in  std_logic_vector (3 downto 0);
      g : in  std_logic_vector (3 downto 0);
      c : in  std_logic;
      z : in  std_logic_vector (0 to 3);
      e : out std_logic) ;
  end component;
  signal a : std_logic_vector (1 downto 0);
  signal b : std_logic_vector (1 downto 0);
  signal f : std_logic_vector (3 downto 0);
  signal g : std_logic_vector (3 downto 0);
  signal c : std_logic;
  signal z : std_logic_vector (0 to 3);
  signal e : std_logic;
begin
  p0 : complex_overload port map (a, b, f, g, c, z, e);
 
  A <= "11"; b <= "01", "00"       after 50 ns;
  f <= "0111"; g <= "1111", "1000" after 50 ns;
  z <= "0111";
  c <= '1', '0'                    after 50 ns, '1' after 100 ns;
end beh;

наверх

4.6.30. Алгоритмические конструкции, переводящиеся при синтезе в элементы памяти и буферы

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
entity BAD is
  port(CLK, DIN : in  std_ulogic;
       DOUT     : out std_ulogic);
end;
 
architecture BEHAVIOR of test is
  signal TMP : std_ulogic;
begin
 
  TMP <=
    DIN when CLK'event and (CLK = '1' or CLK = '0')
    else TMP;
  DOUT <= TMP;
end;

entity example_LATCH is
  port(
    inp_sig, ena : in  bit;
    out_sig      : out bit);
end example_LATCH;
 
architecture beh of example_LATCH is
begin
  process (inp_sig, ena)
 
  begin
    if (ena = '1')then
      out_sig <= inp_sig;
    end if;
  end process;
end beh;

library IEEE;
use IEEE.STD_LOGIC_1164. all;
entity three_state is
  port(
    inp_sig : in  std_logic;
    ena     : in  std_logic;
    out_sig : out std_logic);
end three_state;
architecture exemplar of three_state is
begin
  out_sig <= inp_sig when ena = '1' else 'Z';
end exemplar;

наверх


наверх
4.7. Синтезируемые описания комбинационных схем
4.7.1. Таблицы истинности (совершенные ДНФ)

entity adder_2 is
  port(
    a1, b1, a2, b2 : in  bit;
    c2, s2, s1     : out bit);
end adder_2;
architecture functional_sdnf of adder_2 is
begin
  c2 <= (not a1 and b1 and a2 and b2)
        or (a1 and not b1 and a2 and not b2)
        or (a1 and not b1 and a2 and b2)
        or (a1 and b1 and not a2 and b2)
        or (a1 and b1 and a2 and not b2)
        or (a1 and b1 and a2 and b2);
 
  s2 <= (not a1 and not b1 and a2 and not b2)
        or (not a1 and not b1 and a2 and b2)
        or (not a1 and b1 and not a2 and b2)
        or (not a1 and b1 and a2 and not b2)
        or (a1 and not b1 and not a2 and not b2)
        or (a1 and not b1 and not a2 and b2)
        or (a1 and b1 and not a2 and not b2)
        or (a1 and b1 and a2 and b2);
 
  s1 <= (not a1 and not b1 and not a2 and b2)
        or (not a1 and not b1 and a2 and b2)
        or (not a1 and b1 and not a2 and not b2)
        or (not a1 and b1 and a2 and not b2)
        or (a1 and not b1 and not a2 and b2)
        or (a1 and not b1 and a2 and b2)
        or (a1 and b1 and not a2 and not b2)
        or (a1 and b1 and a2 and not b2);
 
end functional_sdnf;

наверх

4.7.2. Системы ДНФ

entity adder_2 is
  port (a1, b1, a2, b2 : in  bit;
        c2, s2, s1     : out bit);
end adder_2;
architecture functional_dnf of adder_2 is
begin
 
  c2 <= (a1 and a2) or (b1 and b2 and a1) or (b1 and b2 and a2);
 
  s2 <= (b1 and b2 and not a1 and not a2)
            or (b1 and b2 and a1 and a2)
            or (not b1 and a1 and not a2)
            or (not b1 and not a1 and a2)
            or (not b2 and a1 and not a2)
            or (not b2 and not a1 and a2);
 
  s1 <= (b1 and not b2) or (not b1 and b2);
end functional_dnf;

наверх

4.7.4. Диаграммы двоичного решения (BDD)

entity bdd_example is
  port (x1, x2, x3 : in  bit;
        f          : out bit); 
end bdd_example;
 
architecture data_flow of bdd_example is
begin
  p0 : process (x1, x2, x3)
    variable z : bit;
  begin
    if (x1 = '0') then
      if (x2 = '0') then z := '0';
      elsif (x2 = '1') then
        if (x3 = '0') then z    := '0';
        elsif (x3 = '1') then z := '1';
        end if;
      end if;
    elsif (x1 = '1') then
      if (x2 = '0') then
        if (x3 = '0') then z    := '0';
        elsif (x3 = '1') then z := '1';
        end if;
      elsif (x2 = '1') then z := '0';
      end if;
    end if;
    f <= z;
  end process;
end data_flow;

наверх

4.8.1. Конечный автомат

library exemplar;
use exemplar.exemplar_1164.all;
entity FSM_struct is
  port (x   : in  bit;
        clk : in  bit;
        y   : out bit_vector (1 to 2));
end FSM_struct;
architecture rtl of fsm_struct is
  type T_state is (a1, a2);
  attribute TYPE_ENCODING_STYLE of T_state :
    type is ONEHOT;
  signal NEXT_state, state : T_state;
begin
  ns : process (state, x)
  begin
    case state is
      when a1 =>
        if (x = '0') then NEXT_state    <= a2; y <= "00";
        -- код y = (y1, y2)
        elsif (x = '1') then NEXT_state <= a1; y <= "10";
        end if;
      when a2 =>
        if (x = '0') then NEXT_state    <= a1; y <= "01";
        elsif (x = '1') then NEXT_state <= a1; y <= "11";
        end if;
    end case;
  end process ns;
  REG : process (clk)
  begin
    if (clk'event and clk = '1') then state <= NEXT_state;
    end if;
  end process REG; end RTL;

-- library exemplar;
-- use exemplar.exemplar_1164.all;
use work.vvv.all;
entity FSM is
  port (z   : in  fsm_in_type;
        clk : in  bit;
        w   : out fsm_out_type);
end FSM;
 
architecture rtl of fsm is
 
  type T_state is (a1, a2);
 
--  attribute TYPE_ENCODING_STYLE of 
--  T_state : type is ONEHOT;
--  T_state : type is BINARY;
 
  signal NEXT_state, state : T_state;
 
begin
  ns : process (state, z)
  begin
    NEXT_state <= state;
    case state is
      when a1 =>
        if (z = z1) then NEXT_state    <= a2; w <= w1;
        elsif (z = z2) then NEXT_state <= a1; w <= w3;
        end if;
      when a2 =>
        if (z = z1) then NEXT_state    <= a1; w <= w2;
        elsif (z = z2) then NEXT_state <= a1; w <= w4;
        end if;
    end case;
  end process ns;
  REG : process (clk)
  begin
    if clk = '1' then
      state <= NEXT_state;
    end if;
  end process REG;
end rtl;

package vvv is
  type fsm_in_type is (z1, z2);
  type fsm_out_type is (w1, w2, w3, w4);
end vvv;
package body vvv is
end vvv;

--  Тест для моделирования автомата FSM
 
use work.vvv.all;
entity TestBench is
end TestBench;
architecture TBArch of TestBench is
  component FSM
    port (z   : in  fsm_in_type;
          clk : in  bit;
          w   : out fsm_out_type);
  end component;
  signal z   : fsm_in_type;
  signal w   : fsm_out_type;
  signal clk : bit;
begin
  p : fsm port map (z, clk, w);
  z <= z1,
       z2 after 50 ns, z1 after 100 ns,
       z2 after 150 ns, z2 after 200 ns,
       z1 after 250 ns;
  clk <= '0',
         '1' after 25 ns, '1' after 50 ns,
         '0' after 75 ns, '1' after 100 ns,
         '0' after 125 ns, '1' after 150 ns,
         '0' after 175 ns, '1' after 200 ns,
         '0' after 225 ns, '1' after 250 ns;
end TBArch;

--  Тест для моделирования синтезированной схемы автомата FSM
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test is end test;
architecture rtl of test is
  component fsm
    port (
      z   : in  std_logic;
      clk : in  std_logic;
      w   : out std_logic_vector (1 downto 0));
  end component;
  signal z   : std_logic;
  signal clk : std_logic;
  signal w   : std_logic_vector (1 downto 0);
begin
  p0 : fsm port map (z, clk, w);
 
  z <= '0', '1' after 50 ns,
         '0' after 100 ns, '1' after 150 ns,
         '1' after 200 ns, '0' after 250 ns;
  clk <= '1',
         '0' after 25 ns,
         '1' after 50 ns,
         '0' after 75 ns,
         '1' after 100 ns,
         '0' after 125 ns,
         '1' after 150 ns,
         '0' after 175 ns,
         '1' after 200 ns,
         '0' after 225 ns,
         '1' after 250 ns;
end rtl;

наверх

4.8.2. Микропрограммный автомат

library exemplar;
use exemplar.exemplar_1164.all;
 
entity Mealy is
  port(x        : in  bit_vector (4 downto 1);
       clk, rst : in  bit;
       y        : out bit_vector (6 downto 1));
end Mealy;
 
architecture rtl of Mealy is
  type T_state is (a1, a2, a3, a4, a5, a6);
  attribute TYPE_ENCODING_STYLE of T_state :
    type is Onehot;
  signal NEXT_state, state : T_state;
begin
  ns : process (state, x)
  begin
    case state is
      when a1 =>
        NEXT_state <= a2;
        y          <= "000101";
      -- код y= (y6, y5, y4, y3, y2, y1)
      -- код x= (x4, x3, x2, x1)
      when a2 =>
        if ((x(1) and not x(2) and not x(3)) = '1') then
          NEXT_state <= a2;
          y          <= "000000";
        elsif (not x(1) = '1') then
          NEXT_state <= a5;
          y          <= "000010";
        elsif ((x(1) and not x(2) and x(3)) = '1') then
          NEXT_state <= a4;
          y          <= "001000";
        elsif ((x(1) and x(2)) = '1') then
          NEXT_state <= a3;
          y          <= "000110";
        end if;
      when a3 =>
        NEXT_state <= a4;
        y          <= "001001";
      when a4 =>
        if (x(2) = '1') then
          NEXT_state <= a6;
          y          <= "010000";
        elsif (not x(2) = '1') then
          NEXT_state <= a1;
          y          <= "000000";
        end if;
      when a5 =>
        if ((x(1) and x(4)) = '1') then
          NEXT_state <= a5;
          y          <= "000000";
        elsif (not x(4) = '1') then
          NEXT_state <= a4;
          y          <= "001001";
        elsif ((not x(1) and x(4)) = '1') then
          NEXT_state <= a1;
          y          <= "100000";
        end if;
      when a6 =>
        NEXT_state <= a1;
        y          <= "100000";
    end case;
  end process ns;
 
  state <=
    a1         when rst = '1' else
    NEXT_state when clk'event and clk = '1'else state;
end rtl;

library exemplar;
use exemplar.exemplar_1164.all;
 
entity Moore is
  port(x        : in bit_vector (4 downto 1);
       clk, rst : in bit;
       y        :out bit_vector (6 downto 1));
end Moore;
 
architecture rtl of Moore is
  type T_state is (a1, a2, a3, a4, a5, a6, a7, a8);
  attribute TYPE_ENCODING_STYLE of T_state : type is Onehot;
  signal NEXT_state, state                 : T_state;
begin
  NEXT_state <=
    a2 when state = a1 else
 
    a6 when state = a2 and x(1) = '0' else
    a3 when state = a2 and x(1) = '1' and x(2) = '1'
    else
    a4 when state = a2 and x(1) = '1' and x(2) = '0'
    and x(3) = '1' else
    a2 when state = a2 and x(1) = '1' and x(2) = '0'
    and x(3) = '0'
    else
    a5 when state = a3 else
 
    a1 when state = a4 and x(2) = '0' else
    a7 when state = a4 else
 
    a1 when state = a5 and x(2) = '0' else
    a7 when state = a5 else
 
    a5 when state = a6 and x(4) = '0' else
    a6 when state = a6 and x(1) = '1' and x(4) = '1' else
    a8 when state = a6 and x(1) = '0' and x(4) = '1'
    else
 
    a8 when state = a7 else
 
    a1 when state = a8 else
    state;
 
  y <=
    "000000" when state = a1 else
    "000101" when state = a2 else
    "000110" when state = a3 else
    "001000" when state = a4 else
    "001001" when state = a5 else
    "000010" when state = a6 else
    "010000" when state = a7 else
    "100000";
  state <= a1 when rst = '1' else
           NEXT_state when clk'event and clk = '1' else state;
 
end rtl;

library exemplar;
use exemplar.exemplar_1164.all;
 
entity Moore is
  port(x        : in bit_vector (4 downto 1);
       clk, rst : in bit;
       y        :out bit_vector (6 downto 1));
end Moore;
architecture rtl of Moore is
  type T_state is (a1, a2, a3, a4, a5, a6, a7, a8);
  attribute TYPE_ENCODING_STYLE of T_state :
    type is Onehot;
  signal NEXT_state, state : T_state;
begin
 
  ns : process (state, x)
  begin
    case state is
      when a1 => NEXT_state <= a2;
      when a2 =>
        if ((x(1) and not x(2) and not x(3)) = '1')
        then NEXT_state <= a2;
        elsif ((x(1) and x(2)) = '1')
        then NEXT_state <= a3;
        elsif ((x(1) and not x(2) and x(3)) = '1')
        then NEXT_state <= a4;
        elsif (not x(1) = '1')
        then NEXT_state <= a6;
        end if;
      when a3 => NEXT_state <= a5;
      when a4 =>
        if (not x(2) = '1') then NEXT_state <= a1;
        elsif (x(2) = '1')
        then NEXT_state                     <= a7;
        end if;
      when a5 =>
        if (not x(2) = '1') then NEXT_state <= a1;
        elsif (x(2) = '1') then NEXT_state  <= a7;
        end if;
      when a6 =>
        if (not x(4) = '1') then NEXT_state <= a5;
        elsif ((x(1) and x(4)) = '1')
        then NEXT_state                     <= a6;
        elsif ((not x(1) and x(4)) = '1')
        then NEXT_state                     <= a8;
        end if;
      when a7 => NEXT_state <= a8;
      when a8 => NEXT_state <= a1;
    end case;
  end process ns;
  y <=
    "000000" when state = a1 else
    "000101" when state = a2 else
    "000110" when state = a3 else
    "001000" when state = a4 else
    "001001" when state = a5 else
    "000010" when state = a6 else
    "010000" when state = a7 else
    "100000";
 
  state <= a1 when rst = '1' else
           NEXT_state when clk'event and clk = '1' else state;
end rtl;

наверх

4.9.1. Генератор синхросигналов

--   Не синтезируемый VHDL-код
 
entity clock_gen is
  generic (Tpw : time := 50 ns;
           Tps : time := 30 ns);                        
  port (ph1, ph2 : out bit);
end clock_gen;
architecture beh of clock_gen is
  constant clock_period : time := 2*(Tpw+Tps);
begin
  clock_driver : process
  begin
    ph1 <= '1', '0' after Tpw;
    ph2 <= '1'      after Tpw+Tps, '0' after Tpw+Tps+Tpw;
    wait for clock_period;              -- используется тип time
  end process clock_driver;
end beh;

--   Тест для моделирования схемы clock_gen
 
entity test is
end test;
 
architecture beh of test is
  component clock_gen
    generic (Tpw : time := 50 ns;
             Tps : time := 30 ns);
    port (ph1, ph2 : out bit);
  end component;
 
  signal ph1, ph2 : bit;
begin
  p0 : clock_gen port map (ph1, ph2);
end beh;

наверх

4.9.2. Дешифратор

library IEEE;
use IEEE.STD_LOGIC_1164. all;
use IEEE.NUMERIC_STD. all;
library exemplar;
use exemplar.exemplar_1164.all;
 
entity Decoder is
  port (enable : in  bit;
        Din    : in  std_logic_vector (2 downto 0);
        Dout   : out std_logic_vector (7 downto 0));
end Decoder;
architecture Synt of Decoder is
begin
  with enable select
    Dout <= sl ("00000001", TO_INTEGER (unsigned(Din)))
    when '1',
    "00000000" when '0';
end Synt;

--   Тест для моделирования схемы Decoder
 
library IEEE;
use IEEE.STD_LOGIC_1164. all;
library work;
use work.exemplar.all;
entity test is
end test;
 
arcitecture beh of test is
component Decoder
  port (enable : in  bit;
        Din    : in  std_logic_vector (2 downto 0);
        Dout   : out std_logic_vector (7 downto 0));
end component;
 
begin
  p0 : Decoder (enable, Din, Dout);
  Din <= "001",
         "010" after 20 ns,
         "011" after 40 ns,
         "100" after 60 ns,
         "101" after 80 ns,
         "110" after 100 ns,
         "111" after 120 ns,
         "000" after 140 ns;
end beh;

наверх

4.9.3. Мультиплексор

entity Mux4 is
  port
    (i          :     bit_vector(3 downto 0);
            sel :     bit_vector(1 downto 0);
            s   : out bit);
end Mux4;
architecture Synthesis_2 of Mux4 is
begin
  with sel select
    s <= i(0) when "00",
    i(1)      when "01",
    i(2)      when "10",
    i(3)      when "11";
end Synthesis_2;

entity Mux4 is
  port
    (i        :     bit_vector(3 downto 0);
          sel :     bit_vector(1 downto 0);
          s   : out bit);
end Mux4;
architecture Synthesis_1 of Mux4 is
begin
  process (sel, i)
  begin
    case sel is
      when "00" => s <= i(0); when "01" => s <= i(1);
      when "10" => s <= i(2); when "11" => s <= i(3);
    end case;
  end process;
end Synthesis_1;

library IEEE;
use ieee.std_logic_1164. all;
use ieee.numeric_std.all;
entity Mux8 is
  port
    (InBus  : in  std_logic_vector(7 downto 0);
     Sel    : in  std_logic_vector(2 downto 0);
     OutBit : out std_logic);
end Mux8;
 
architecture Synthesis_1 of Mux8 is
begin
  process (InBus, Sel)
  begin
    OutBit <= InBus(TO_INTEGER (unsigned(Sel)));
  end process;
end Synthesis_1;

library IEEE;
use ieee.std_logic_1164. all;
 
entity Mux8 is port
                 (InBus  : in  std_logic_vector(7 downto 0);
                  Sel    : in  integer range 0 to 7;
                  OutBit : out std_logic);
end Mux8;
architecture Synthesis_1 of Mux8 is
begin
  process (InBus, Sel)
  begin
    OutBit <= InBus(Sel);
  end process;
end Synthesis_1;

наверх

4.9.4. Демультиплексор

entity demux_n is
  generic (N : natural := 4);
  port
    (x  : in  bit_vector(0 to N-1);
      w : in  bit;
      y : out bit_vector(0 to 2**N - 1));
end demux_n;
 
architecture beh of demux_n is
  signal i                      : integer range 0 to 2**N-1;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function output_j (
    constant N : natural;
    signal j   : integer;
    signal w   : bit) 
    return bit_vector
  is
    variable z : bit_vector(0 to 2**N - 1);
  begin
    for k in 0 to 2**N-1 loop
      if ((k = j) and (w = '1')) then z(k) := '1';
      else z(k)                            := '0';
      end if;
    end loop;
    return z;
  end output_j;
 
begin
  i <= bin_to_int(x);
  y <= output_j(N, i, w);
end beh;

--   Тест для моделирования схемы demux_n
 
entity test_demux_n is
end test_demux_n;
architecture beh of test_demux_n is
  component demux_n
    generic (N : natural := 4);
    port
      (x  : in  bit_vector(0 to N-1);
        w : in  bit;
        y : out bit_vector(0 to 2**N - 1));
  end component;
  signal x : bit_vector(0 to 3);
  signal w : bit;
  signal y : bit_vector(0 to 15);
begin
  p0 : demux_n port map (x, w, y);
  x <= "1000", "0011" after 50 ns,
       "0111" after 100 ns, "1111" after 120 ns;
  w <='0', '1' after 40 ns, '0' after 80 ns,
      '1' after 100 ns;
end beh;

наверх

4.9.5. Постоянное запоминающее устройство

package pack_ROM is
  type seven_segment is array (6 downto 0) of bit;
  type rom_type is array (natural range <>) of seven_segment;
  constant hex_to_7 : rom_type (0 to 15) :=
    ("0111111",                         -- адрес 0
     "0011000",                         -- адрес 1
     "1101111",                         -- адрес 2 
     "1111100",                         -- адрес 3 
     "1011010",                         -- адрес 4 
     "1110110",                         -- адрес 5 
     "1110111",                         -- адрес 6 
     "0011100",                         -- адрес 7 
     "1111111",                         -- адрес 8
     "1111110",                         -- адрес 9
     "1011111",                         -- адрес 10
     "1110011",                         -- адрес 11
     "0100111",                         -- адрес 12
     "1111001",                         -- адрес 13
     "1100111",                         -- адрес 14
     "1000111");                        -- адрес 15
end pack_ROM;
 
package body pack_ROM is
end pack_ROM;

library work;
use work.pack_rom.all;
entity ROM7 is
  port (addr     : in  integer range 0 to 15;
        out_word : out seven_segment); 
end ROM7;
architecture str of ROM7 is
begin
  out_word <= hex_to_7 (addr);
end str;

--   Тест для моделирования схемы ROM7
 
library work;
use work.pack_rom.all;
entity test_ROM7 is
end test_ROM7;
 
architecture str of test_ROM7 is
  component ROM7
    port (addr     : in  integer range 0 to 15;
          out_word : out seven_segment); 
  end component;
  signal addr     : integer range 0 to 15;
  signal out_word : seven_segment;
begin
  p0 : ROM7 port map (addr, out_word);
  addr <= 0, 1 after 50 ns, 8 after 100 ns,
          9 after 200 ns, 15 after 300 ns;
end str;

наверх

4.9.6. Двухразрядный сумматор

library work;
use work.pack_adder_ROM.all;
entity adder_2 is
  port (a1, b1, a2, b2 : in  bit;
        c2, s2, s1     : out bit);
end adder_2;
architecture functional_rom of adder_2 is
  signal addr     : integer range 0 to 15;
  signal out_word : three_segment;
begin
 
  addr     <= bin4_to_int (a1, b1, a2, b2);
  out_word <= table_to_3 (addr);
  c2       <= out_word(2);
  s2       <= out_word(1);
  s1       <= out_word(0);
end functional_rom;

package pack_adder_ROM is
 
  type three_segment is array (2 downto 0) of bit;
  type rom_type is array (natural range <>) of three_segment;
  constant table_to_3 : rom_type (0 to 15) :=
    ("000",                             -- 0+0
     "001",                             -- 0+1
     "010",                             -- 0+2 
     "011",                             -- 0+3 
     "001",                             -- 1+0 
     "010",                             -- 1+1 
     "011",                             -- 1+2 
     "100",                             -- 1+3 
     "010",                             -- 2+0
     "011",                             -- 2+1
     "100",                             -- 2+2
     "101",                             -- 2+3
     "011",                             -- 3+0
     "100",                             -- 3+1
     "101",                             -- 3+2
     "110") ;                           -- 3+3
  function bin4_to_int (signal w3, w2, w1, w0 : bit)
    return integer;
end pack_adder_ROM;
 
package body pack_adder_ROM is
  function bin4_to_int (signal w3, w2, w1, w0 : bit)
    return integer is
    variable sum : integer := 0;
  begin
    if w0 = '1' then sum := 1;       else sum := 0; end if;
    if w1 = '1' then sum := sum + 2; else sum := sum;
                                     end if;
    if w2 = '1' then sum := sum + 4; else sum := sum;
                                     end if;
    if w3 = '1' then sum := sum + 8; else sum := sum;
                                     end if;
    return sum;
  end bin4_to_int;
end pack_adder_ROM;

наверх

4.9.7. Четырехразрядный сумматор

entity adder_4 is
  port (x, y : in  bit_vector(3 downto 0);
         z   : out bit_vector(4 downto 0));
end adder_4;
 
architecture beh of adder_4 is
  function vector_adder_4 (x : bit_vector(3 downto 0);
                           y : bit_vector(3 downto 0))
    return bit_vector is
    variable carry  : bit;
    variable result : bit_vector(4 downto 0);
  begin
    carry := '0';
    for i in 0 to 3 loop
      result (i) := x(i) xor y(i) xor carry;
      carry      := (carry and (x(i) or y(i))) or (x(i) and y(i));
    end loop;
    result (4) := carry;
    return result;
  end vector_adder_4;
 
begin
  z <= vector_adder_4 (x, y);
end beh;

entity adder_4_data_flow is
  port (x, y : in  bit_vector (0 to 3);
        z    : out bit_vector (0 to 4));
end adder_4_data_flow;
architecture func of adder_4_data_flow is
  signal c : bit_vector (1 to 3);
begin
  z(0) <= (x(0) and not y(0)) or (not x(0) and y(0));
  c(1) <= x(0) and y(0);
 
  z(1) <= (not x(1) and not y(1) and c(1)) or
          (x(1) and y(1) and c(1)) or
          (x(1) and not y(1) and not c(1)) or
          (not x(1) and y(1) and not c(1));
  c(2) <= (x(1) and y(1)) or (x(1) and c(1)) or (y(1) and c(1));
 
  z(2) <= (not x(2) and not y(2) and c(2)) or
          (x(2) and y(2) and c(2)) or
          (x(2) and not y(2) and not c(2)) or
          (not x(2) and y(2) and not c(2));
  c(3) <= (x(2) and y(2)) or (x(2) and c(2)) or (y(2) and c(2));
 
  z(3) <= (not x(3) and not y(3) and c(3)) or
          (x(3) and y(3) and c(3)) or
          (x(3) and not y(3) and not c(3)) or
          (not x(3) and y(3) and not c(3));
  z(4) <= (x(3) and y(3)) or (x(3) and c(3)) or (y(3) and c(3));
 
end func;

library IEEE;
use IEEE.STD_LOGIC_1164. all;
use IEEE.NUMERIC_STD. all;
library exemplar;
use exemplar.exemplar_1164.all;
 
entity adder_4_ex is
  port (x, y : in  std_logic_vector(3 downto 0);
         z   : out std_logic_vector(4 downto 0));
end adder_4_ex;
 
architecture beh of adder_4_ex is
begin
  z <= add (x, y);
end beh;

entity adder_4_integer is
  port(
    x1, x2 : in  integer range 0 to 15;
    y      : out integer range 0 to 30);
end adder_4_integer;
architecture beh of adder_4_integer is
begin
  y <= x1 + x2;
end beh;

наверх

4.9.8. Многоразрядный сумматор

entity add2 is
  port (c1, a1, a2 : in  bit;
        c2, s2     : out bit);
end add2;
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and a1 and (not a2)) or
        (c1 and (not a1)and (not a2)) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

entity adder_N is
  generic (N : natural := 4);
  port (a, b : in  bit_vector (0 to N-1);
        s    : out bit_vector (0 to N-1);
        c    : out bit);
end adder_N;
 
architecture func_1 of adder_N is
  component add2
    port(c1, a1, a2 : in  bit;
         c2, s2     : out bit);
  end component;
  signal c_in : bit_vector (0 to N);
 
begin
  c_in(0) <= '0';
  adder : for i in 0 to N-1 generate
    all_bit : add2 port map (c1 => c_in(i), a1 => a(i), a2 => b(i),
                            c2  => c_in(i+1), s2 => s(i));
  end generate adder;
  c <= c_in(N);
end func_1;

наверх

4.9.9. Двухразрядный умножитель

entity add1 is
  port (b1, b2 : in  bit;
        c1, s1 : out bit);
end add1;
 
architecture struct_1 of add1 is
begin
  s1 <= ((b1 and (not b2)) or ((not b1) and b2));
  c1 <= b1 and b2;
end struct_1;
 
architecture struct_2 of add1 is
begin
  s1 <= b1 xor b2;
  c1 <= b1 and b2;
end struct_2;

library work;
use work.vv_vls.all;
entity mult_2 is
  port (s1, s0, r1, r0 : in  bit;
        t3, t2, t1, t0 : out bit);
end mult_2;
 
architecture functional of mult_2 is
 
  signal ss, rr : integer range 0 to 3;
  signal tt     : integer range 0 to 9;
  signal tt_sig : bit_vector (0 to 3);
 
begin
 
  ss     <= bin2_to_int(s0, s1);
  rr     <= bin2_to_int(r0, r1);
  tt     <= ss*rr;                      -- перемножение целых чисел 
  tt_sig <= int_to_bin4(tt);
 
  t0 <= tt_sig(0);
  t1 <= tt_sig(1);
  t2 <= tt_sig(2);
  t3 <= tt_sig(3);
end functional;

entity mult_2_pure is
  port(
    x1, x2 : in  integer range 0 to 3;
    y      : out integer range 0 to 9);
end mult_2_pure;
 
architecture str of mult_2_pure is
begin
  y <= x1 * x2;
end str;

entity mult_2 is
  port (s1, s0, r1, r0 : in  bit;
        t3, t2, t1, t0 : out bit);
end mult_2;
 
architecture struct of mult_2 is
  component
    add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
 
  signal p1, p2, p3, p4 : bit;
begin
  t0 <= r0 and s0;
  p2 <= r0 and s1;
  p1 <= r1 and s0;
  p4 <= r1 and s1;
 
  circ1 : add1
    port map (b1 => p1, b2 => p2, c1 => p3, s1 => t1);
  circ2 : add1
    port map (b1 => p3, b2 => p4, c1 => t3, s1 => t2);
end struct;

package vv_vls is
  function bin2_to_int (signal w2, w1 : bit)
    return integer;
  function int_to_bin4
    (signal INPUT : integer)
    return bit_vector;
  constant N                    : integer := 4;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer;
  type in_array is array (natural range 1 to 4,
                          natural range 1 to 4)  -- двумерный массив
    of integer range 0 to 7;
  type out_array is array (natural range 1 to 4,
                           natural range 1 to 4)
    of integer range 0 to 256;
 
  type fsm_in_type is (z1, z2);         -- перечислимый тип
  type fsm_out_type is (w1, w2, w3, w4);
  type states is (a1, a2);
end vv_vls;
 
package body vv_vls is                  -- тело пакета
  function bin_to_int                   -- функция
    (signal x    : bit_vector (0 to N-1))
    -- левый разряд старший, возрастающий диапазон
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function bin2_to_int                  -- функция
    (signal w2, w1 : bit)               --  w2 - старший разряд
    return integer is
    variable sum   : integer := 0;
  begin
    if w1 = '1' then
      sum := 1;
    else
      sum := 0;
    end if;
    if w2 = '1' then
      sum := sum+2;
    else
      sum := sum;
    end if;
    return sum;
  end bin2_to_int;
 
  function int_to_bin4                  -- функция
    (signal INPUT   : integer)
    return bit_vector is                -- правый разряд старший
    -- возрастающий диапазон
    variable fout   : bit_vector(0 to 3);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 3 downto 0 loop
      temp_b := temp_a/(2**i);
      temp_a := temp_a rem (2**i);
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_to_bin4;
 
end vv_vls;

наверх

4.9.10. Инкрементор, декрементор

 
library Work;
use work.perfom.all;
entity incrementor_N is
  port (A : in  bit_vector (0 to N-1);
        B : out bit_vector (0 to N-1));
end incrementor_N;
 
architecture functional of incrementor_N is
  signal ss : integer;
  signal tt : integer;
begin
 
  ss <= bin_to_int(A);
  -- преобр. типа bit_vector в тип integer
  tt <= ss+1;                           -- инкрементор 
-- tt <= ss-1;         -- декрементор
-- B<=int_perfom_bin(tt); -- преобр. типа integer в тип
--  bit_vector
end functional;
 
package perfom is
 
  constant N                    : integer := 5;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer;
  function int_perfom_bin
    (signal INPUT : integer)
    return bit_vector;
 
end perfom;
 
package body perfom is
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function int_perfom_bin
-- левый разряд старший, возрастающий диапазон 
    (signal INPUT   : integer)
    return bit_vector is
    variable fout   : bit_vector(0 to N-1);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 0 to N-1 loop
      temp_b := temp_a/(2**(N-1-i));
      temp_a := temp_a rem (2**(N-1-i));
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_perfom_bin;
 
end perfom;

package perfom is
 
  constant N                    : integer := 5;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer;
  function int_perfom_bin
    (signal INPUT : integer)
    return bit_vector;
 
end perfom;
 
package body perfom is
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function int_perfom_bin
-- левый разряд старший, возрастающий диапазон 
    (signal INPUT   : integer)
    return bit_vector is
    variable fout   : bit_vector(0 to N-1);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 0 to N-1 loop
      temp_b := temp_a/(2**(N-1-i));
      temp_a := temp_a rem (2**(N-1-i));
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_perfom_bin;
 
end perfom;

наверх

4.9.11. Компаратор

library Work;
use work.perfom.all;
entity comparator is
  port (A, B : in  bit_vector (0 to N-1);
        F    : out bit);
end comparator;
 
architecture functional of comparator is
 
  signal ss : integer;
  signal tt : integer;
begin
 
  ss <= bin_to_int(A);  -- преобразование типа bit_vector в тип integer
  tt <= bin_to_int(B);                  -- преобразование типа 
  -- bit_vector в тип integer
  p0 : process (ss, tt)
  begin
    if (A > B) then F <= '1';
    elsif (A          <= B) then F <= '0';
    end if;
  end process;
end functional;

package perfom is
 
  constant N                    : integer := 5;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer;
  function int_perfom_bin
    (signal INPUT : integer)
    return bit_vector;
 
end perfom;
 
package body perfom is
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function int_perfom_bin
-- левый разряд старший, возрастающий диапазон 
    (signal INPUT   : integer)
    return bit_vector is
    variable fout   : bit_vector(0 to N-1);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 0 to N-1 loop
      temp_b := temp_a/(2**(N-1-i));
      temp_a := temp_a rem (2**(N-1-i));
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_perfom_bin;
 
end perfom;

наверх

4.9.12. Программируемая логическая матрица

library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity mod_PLA_synt is
  port (invec         : in  std_logic_vector (3 downto 0);
        result_vector : out std_logic_vector (2 downto 0));
 
end mod_PLA_synt;
architecture DNF of mod_PLA_synt is
begin
  result_vector (2) <= invec(3)
                       or (not invec(3) and not invec(2) and not invec(1) and not invec(0));
 
  result_vector (1) <= (not invec(3) and not invec(2) and invec(1))
                       or (not invec(3) and not invec(2) and not invec(1) and invec(0))
                       or (not invec(3) and not invec(2) and not invec(1) and not invec(0));
 
  result_vector (0) <= (not invec(3) and invec(2))
                       or (not invec(3) and not invec(2) and not invec(1) and invec(0))
                       or (not invec(3) and not invec(2) and not invec(1) and not invec(0));
 
end DNF;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.pack.all;
 
entity mod_PLA_synt is
  port (invec         : in  std_logic_vector (3 downto 0);
        -- входные порты есть
        result_vector : out std_logic_vector (2 downto 0));
end mod_PLA_synt;
 
architecture beh of mod_PLA_synt is
 
  constant pla_example : std_logic_pla (4 downto 0, 6 downto 0) :=
    ("1---100",                         -- промежуточная шина 1
     "01--001",                         -- промежуточная шина 2
     "001-010",                         -- промежуточная шина 3
     "0001011",                         -- промежуточная шина 4
     "0000111") ;                       -- промежуточная шина 5
 
begin
  pla_table (invec, result_vector, pla_example);
end beh;

--   Не синтезируемый VHDL-код
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.pack.all;
 
entity mod_PLA is
  port (result_vector :
        out std_logic_vector (2 downto 0));
-- входных портов нет
end mod_PLA;
 
architecture beh of mod_PLA is
 
  constant pla_example : std_logic_pla (4 downto 0, 6 downto 0) :=
    ("1---100",                         -- промежуточная шина 1
     "01--001",                         -- промежуточная шина 2
     "001-010",                         -- промежуточная шина 3
     "0001011",                         -- промежуточная шина 4
     "0000111") ;                       -- промежуточная шина 5
  constant test_vector : std_logic_vector (3 downto 0) := "0100";
begin
  pla_table (test_vector, result_vector, pla_example);
end beh;
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package pack is
  type std_logic_pla is array (natural range <>, natural range <>)
    of std_logic;
 
  procedure pla_table (constant invec :     std_logic_vector;
                       signal outvec  : out std_logic_vector;
                       constant table :     std_logic_pla);
 
end pack;
package body pack is
 
  procedure pla_table (constant invec :     std_logic_vector;
                       signal outvec  : out std_logic_vector;
                       constant table :     std_logic_pla) is
    variable x : std_logic_vector (table'range(1));
    -- промежуточные шины
    variable y : std_logic_vector (outvec'range);
    -- выходы
    variable b : std_logic;
  begin
    assert (invec'length + outvec'length = table'length(2))
      report "Size of Inputs and Outputs do not match table size"
      severity error;
    -- Вычисления в матрице И
    x := (others => '1');
    for i in table'range(1) loop
      for j in invec'range loop
        b := table (i, table'left(2)-invec'left+j);
        if (b = '1') then
          x(i) := x(i) and invec (j);
        elsif (b = '0') then
          x(i) := x(i) and not invec(j);
        end if;
      end loop;
    end loop;
    -- Вычисления в матрице ИЛИ 
    y := (others => '0');
    for i in table'range(1) loop
      for j in outvec'range loop
        b := table(i, table'right(2)-outvec'right+j);
        if (b = '1') then
          y(j) := y(j) or x(i);
        end if;
      end loop;
    end loop;
    outvec <= y;
  end pla_table;
 
end pack;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
package pack is
  type std_logic_pla is array (natural range <>, natural range <>)
    of std_logic;
 
  procedure pla_table (constant invec :     std_logic_vector;
                       signal outvec  : out std_logic_vector;
                       constant table :     std_logic_pla);
 
end pack;
package body pack is
 
  procedure pla_table (constant invec :     std_logic_vector;
                       signal outvec  : out std_logic_vector;
                       constant table :     std_logic_pla) is
    variable x : std_logic_vector (table'range(1));
    -- промежуточные шины
    variable y : std_logic_vector (outvec'range);
    -- выходы
    variable b : std_logic;
  begin
    assert (invec'length + outvec'length = table'length(2))
      report "Size of Inputs and Outputs do not match table size"
      severity error;
    -- Вычисления в матрице И
    x := (others => '1');
    for i in table'range(1) loop
      for j in invec'range loop
        b := table (i, table'left(2)-invec'left+j);
        if (b = '1') then
          x(i) := x(i) and invec (j);
        elsif (b = '0') then
          x(i) := x(i) and not invec(j);
        end if;
      end loop;
    end loop;
    -- Вычисления в матрице ИЛИ 
    y := (others => '0');
    for i in table'range(1) loop
      for j in outvec'range loop
        b := table(i, table'right(2)-outvec'right+j);
        if (b = '1') then
          y(j) := y(j) or x(i);
        end if;
      end loop;
    end loop;
    outvec <= y;
  end pla_table;
 
end pack;

--  Тест для моделирования схемы mod_PLA_synt
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.pack.all;
 
entity test is
end test;
 
architecture beh of test is
  component mod_PLA_synt
    port (invec         : in  std_logic_vector (3 downto 0);
          result_vector : out std_logic_vector (2 downto 0));
  end component;
  signal invec         : std_logic_vector (3 downto 0);
  signal result_vector : std_logic_vector (2 downto 0);
begin
 
  p0 : mod_pla_synt port map (invec, result_vector);
 
  invec <= "0000", "0001" after 50 ns;
end beh;

--   Тест для моделирования схемы mod_PLA
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.pack.all;
 
entity test is
end test;
 
architecture beh of test is
  component mod_PLA
    port (result_vector :
          out std_logic_vector (2 downto 0));
  end component;
  signal result_vector : std_logic_vector (2 downto 0);
begin
  p0 : mod_pla port map (result_vector);
end beh;

наверх

4.9.13. D-триггер

--  Синтезированный VHDL-код схемы dlatch
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package components is
  procedure DFFPC (
    constant data   : in  std_logic;
    constant preset : in  std_logic;
    constant clear  : in  std_logic;
    signal clk      : in  std_logic;
    signal q        : out std_logic) ;
 
  component GND
    port (
      Y : out std_logic) ;
  end component;
end components;
 
 
package body components is
  procedure DFFPC (
    constant data   : in  std_logic;
    constant preset : in  std_logic;
    constant clear  : in  std_logic;
    signal clk      : in  std_logic;
    signal q        : out std_logic)
  is begin
       if (preset = '1') then
         q <= '1';
       elsif (clear = '1') then
         q <= '0';
       elsif (clk'event and clk'last_value = '0' and clk = '1') then
         q <= data and data;            -- takes care of q<='X' if data='Z'
       end if;
       if ((clear /= '1' or preset /= '1') and clk /= '0' and clk /= '1') then
         q <= 'X';
       end if;
     end DFFPC;
     end components;
 
       library IEEE;
       use IEEE.STD_LOGIC_1164.all;
 
       entity dlatch is
         port (
           d   : in  std_logic;
           clk : in  std_logic;
           q   : out std_logic) ;
       end dlatch;
 
       architecture functional of dlatch is
         signal GND0 : std_logic;
 
       begin
         work.components.DFFPC (d, GND0, GND0, clk, q);
         ix3 : work.components.GND port map (Y => GND0);
       end functional;

entity d_latch is
  port(d, clk : in  bit;
       q      : out bit);
end d_latch;
architecture structural of d_latch is
  component NAND2
    port (i1, i2 : in bit; o : out bit);
  end component;
  signal A, B, Y1, Y2 : bit;
begin
  DD1 : NAND2
    port map (d, clk, A);
  DD2 : NAND2
    port map (A, clk, B);
  DD3 : NAND2
    port map (A, Y2, Y1);
  DD4 : NAND2
    port map (B, Y1, Y2);
  q <= Y1;
end structural;

entity dlatch is
  port(
    d, clk : in  bit;
    q      : out bit);
end dlatch;
 
architecture functional of dlatch is
begin
  dff : process
  begin
    wait until clk'event and clk = '1';
    Q <= D;
  end process;
end functional;

library IEEE;
use IEEE.std_logic_1164.all;
entity GND is
  port(Y : out std_logic);
end;
architecture GND_arch of GND is
begin
  Y <= '0';
end GND_arch;

entity NAND2 is
  port(i1, i2 : in bit; o : out bit);
end NAND2;
architecture behavior of NAND2 is
begin
  o <=not(i1 and i2);
 
end behavior;

--   Тест для моделирования схемы dlatch
 
entity test_dlatch is
end test_dlatch;
 
architecture func of test_dlatch is
  component dlatch port
                      (d, clk : in  bit;
                       q      : out bit);
  end component;
  signal d, clk, q : bit;
 
begin
  p1 : dlatch port map (d, clk, q);
-- p1 : d_latch port map (d, clk, q); 
--(для моделирования  структурного описания)
  p2 : process
    variable number : integer := 20;
    variable period : time    := 100 ns;
  begin
    for i in 1 to number loop
      CLK <= transport '1'; wait for period/2;
      CLK <= transport '0'; wait for period/2;
    end loop;
  end process p2;
  p3 : process
    variable period : time := 100 ns;
  begin
    d <= '1'; wait for period;
    d <= '0'; wait for 2*period + period/2;
    d <= '1'; wait for period;
    d <= '0'; wait for 2*period + period/2;
  end process p3;
end func;

наверх

4.9.14. Параллельный регистр

entity REGISTR_N_1mod is
  generic (N : natural := 3);
  port (DATA   : in  bit_vector (0 to N);
        clk    : in  bit;
        OUTPUT : out bit_vector (0 to N)); 
end REGISTR_N_1mod;
 
architecture beh of REGISTR_N_1mod is
begin
  REG : process (clk)
  begin
    if (clk'event and clk = '1') then
      OUTPUT <= DATA;
    end if;
  end process;
 
end beh;

entity REGISTR_N_2mod is
  generic (N : natural := 3);
  port (DATA   : in  bit_vector (0 to N);
        clk    : in  bit;
        OUTPUT : out bit_vector (0 to N)); 
end REGISTR_N_2mod;
 
architecture beh of REGISTR_N_2mod is
begin
  REG : process
  begin
    wait until clk'event and clk = '1';
    OUTPUT <= DATA;
  end process;
 
end beh;

наверх

4.9.15. Сдвиговый регистр

entity DFF is
  port (
    RSTn, CLK, D : in  bit;
    Q            : out bit);
end DFF;
architecture RTL of DFF is
begin
  process (RSTn, CLK)
  begin
    if (RSTn = '0') then
      Q <= '0';
    elsif (CLK'event and CLK = '1') then
      Q <= D;
    end if;
  end process;
end RTL;

entity SHIFT is
  port (
    RSTn, CLK, SI : in  bit;
    SO            : out bit);
end SHIFT;
 
architecture RTL3 of SHIFT is
  component DFF
    port (
      RSTn, CLK, D : in  bit;
      Q            : out bit);
  end component;
  signal T : bit_vector(8 downto 0);
--  декларация сигнала T 
begin
  T(8) <= SI;
  SO   <= T(0);
  g0 : for i in 7 downto 0 generate
    allbit : DFF
      port map (RSTn => RSTn, CLK => CLK, D => T(i+1), Q => T(i));
  end generate;
end RTL3;

наверх

4.9.16. Счетчик

entity counter_3 is
  port (
    RSTn, CLK, EN, PL : in  bit;
    DATA              : in  integer range 0 to 7;
    COUNT             : out integer range 0 to 7);
end counter_3;
 
architecture beh of counter_3 is
  signal COUNT_VALUE : integer range 0 to 7;
begin
  p0 : process (RSTn, CLK)
  begin
    if (RSTn = '0') then
      COUNT_VALUE <= 0;
    elsif (CLK'event and CLK = '1') then
      if (PL = '1') then
        COUNT_VALUE <= DATA;
      elsif (EN = '1') then
        if (COUNT_VALUE = 7) then
          COUNT_VALUE <= 0;
        else
          COUNT_VALUE <= COUNT_VALUE + 1;
        end if;
      end if;
    end if;
  end process;
  COUNT <= COUNT_VALUE;
end beh;

--  Тест для моделирования схемы counter_3
 
entity test is
end test;
 
architecture beh of test is
 
  component counter_3
    port (
      RSTn, CLK, EN, PL : in  bit;
      DATA              : in  integer range 0 to 7;
      COUNT             : out integer range 0 to 7);
  end component;
 
  signal RSTn, CLK, EN, PL : bit;
  signal DATA              : integer range 0 to 7;
  signal COUNT             : integer range 0 to 7;
 
begin
 
  p0 : counter_3 port map (RSTn, CLK, EN, PL, DATA, COUNT);
  RSTn <= '1';
  PL   <= '0';                          -- рис. 4.60,а
-- PL <= '1';       -- рис. 4.60,б
  EN   <= '1';
 
  p1 : process
    variable number   : integer := 40;
    variable period_1 : time    := 30 ns;
  begin
    for i in 1 to number loop
      CLK <= transport '1'; wait for period_1/2;
      CLK <= transport '0'; wait for period_1/2;
    end loop;
  end process p1;
 
  p2 : process
    variable number   : integer := 40;
    variable period_2 : time    := 20 ns;
  begin
    for i in 1 to number loop
      DATA <= 1; wait for period_2;
      DATA <= 2; wait for period_2 + period_2/2;
    end loop;
  end process p2;
 
end beh;

наверх

4.10.3. Использование конфигураций

entity add1 is
  port (b1, b2 : in  bit;
        c1, s1 : out bit);
end add1;
 
architecture struct_1 of add1 is
begin
  s1 <= ((b1 and (not b2)) or ((not b1) and b2));
  c1 <= b1 and b2;
end struct_1;
 
architecture struct_2 of add1 is
begin
  s1 <= b1 xor b2;
  c1 <= b1 and b2;
end struct_2;

entity add2 is
  port (c1, a1, a2 : in  bit;
        c2, s2     : out bit);
end add2;
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and a1 and (not a2)) or
        (c1 and (not a1)and (not a2)) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

entity adder_2 is
  port (a1, b1, a2, b2 : in  bit;
        c2, s2, s1     : out bit);
end adder_2;
 
architecture struct_1 of adder_2 is
  component
    add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
  component add2
    port(c1, a1, a2 : in  bit;
         c2, s2     : out bit);
  end component;
  signal c1 : bit;
 
begin
  circ1 : add1
    port map (b1, b2, c1, s1);
  circ2 : add2
    port map (c1, a1, a2, c2, s2);
end struct_1;

configuration config_mixed_vlsi_1 of vlsi_1 is
  for structure
    for circ2 : mult_2
      use entity work.mult_2(struct);
      for struct
        for all : add1
          use entity work.add1(struct_2);
        end for;
      end for;
    end for;
    for circ3 : adder_2
      use entity work.adder_2(functional_dnf);
    end for;
  end for;
end config_mixed_vlsi_1;

configuration config_pure_functional_vlsi_1 of vlsi_1 is
  for structure
    for circ2 : mult_2
      use entity work.mult_2(functional);
    end for;
    for circ3 : adder_2
      use entity work.adder_2(functional_rom);
    end for;
  end for;
end config_pure_functional_vlsi_1;

configuration config_str_config_adder_2 of vlsi_1 is
  for structure
    for circ2 : mult_2
      use entity work.mult_2(struct);
      for struct
        for all : add1
          use entity work.add1(struct_1);
 
        end for;
      end for;
    end for;
    for circ3 : adder_2
      use configuration work.config_1_adder_2; end for;
  end for;
end config_str_config_adder_2;

configuration config_structure_vlsi_1 of vlsi_1 is
  for structure
    for circ2 : mult_2
      use entity work.mult_2(struct);
      for struct
        for all : add1
          use entity work.add1(struct_2);
        end for;
      end for;
    end for;
    for circ3 : adder_2
      use entity work.adder_2(struct_1);
      for struct_1
        for all : add1
          use entity work.add1(struct_1);
        end for;
        for all : add2
          use entity work.add2(struct_1);
        end for;
      end for;
    end for;
  end for;
end config_structure_vlsi_1;

entity mult_2 is
  port (s1, s0, r1, r0 : in  bit;
        t3, t2, t1, t0 : out bit);
end mult_2;
 
architecture struct of mult_2 is
  component
    add1
    port (b1, b2 : in  bit;
          c1, s1 : out bit);
  end component;
 
  signal p1, p2, p3, p4 : bit;
begin
  t0 <= r0 and s0;
  p2 <= r0 and s1;
  p1 <= r1 and s0;
  p4 <= r1 and s1;
 
  circ1 : add1
    port map (b1 => p1, b2 => p2, c1 => p3, s1 => t1);
  circ2 : add1
    port map (b1 => p3, b2 => p4, c1 => t3, s1 => t2);
end struct;

package vv_vls is
  function bin2_to_int (signal w2, w1 : bit)
    return integer;
  function int_to_bin4
    (signal INPUT : integer)
    return bit_vector;
  constant N                    : integer := 4;
  function bin_to_int (signal x : bit_vector (0 to N-1))
    return integer;
  type in_array is array (natural range 1 to 4,
                          natural range 1 to 4)  -- двумерный массив
    of integer range 0 to 7;
  type out_array is array (natural range 1 to 4,
                           natural range 1 to 4)
    of integer range 0 to 256;
 
  type fsm_in_type is (z1, z2);         -- перечислимый тип
  type fsm_out_type is (w1, w2, w3, w4);
  type states is (a1, a2);
end vv_vls;
 
package body vv_vls is                  -- тело пакета
  function bin_to_int                   -- функция
    (signal x    : bit_vector (0 to N-1))
    -- левый разряд старший, возрастающий диапазон
    return integer is
    variable sum : integer := 0;
  begin
    for i in 0 to N-1 loop
      if (x(i) = '1') then sum := sum + 2**(N-1-i);
      else null;
      end if;
    end loop;
    return sum;
  end bin_to_int;
 
  function bin2_to_int                  -- функция
    (signal w2, w1 : bit)               --  w2 - старший разряд
    return integer is
    variable sum   : integer := 0;
  begin
    if w1 = '1' then
      sum := 1;
    else
      sum := 0;
    end if;
    if w2 = '1' then
      sum := sum+2;
    else
      sum := sum;
    end if;
    return sum;
  end bin2_to_int;
 
  function int_to_bin4                  -- функция
    (signal INPUT   : integer)
    return bit_vector is                -- правый разряд старший
    -- возрастающий диапазон
    variable fout   : bit_vector(0 to 3);
    variable temp_a : integer := 0;
    variable temp_b : integer := 0;
  begin
    temp_a := INPUT;
    for i in 3 downto 0 loop
      temp_b := temp_a/(2**i);
      temp_a := temp_a rem (2**i);
      if (temp_b = 1) then
        fout(i) := '1';
      else
        fout(i) := '0';
      end if;
    end loop;
    return fout;
  end int_to_bin4;
 
end vv_vls;

library work;
use work.vv_vls.all;
 
entity test_VLSI_1 is
end test_VLSI_1;
 
architecture test of test_vlsi_1 is
  component vlsi_1
    port (a2, a1, b2, b1, x : in  bit;
          d4, d3, d2, d1    : out bit);
  end component;
 
 
  signal a2, a1, b2, b1, x, d4, d3, d2, d1 : bit;
  signal s                                 : bit_vector (0 to 3);
begin
  p : vlsi_1
    port map (a2 => a2, a1 => a1, b2 => b2, b1 => b1, x => x,
              d4 => d4, d3 => d3, d2 => d2, d1 => d1);
 
  a2 <= '1' after 25 ns; a1 <= '0' after 25 ns;
  b2 <= '1' after 25 ns; b1 <= '1' after 25 ns;
  x  <= '0' after 25 ns;
  s  <= (d4, d3, d2, d1);
  step1 : process (s)
    variable number : integer range 0 to 15;
  begin
    number := bin_to_int(s);
    if (number /= 5) then
      assert false report "bad (2+3/=5)" severity error;
    end if;
    if (number = 5) then
      assert false report "good (2+3=5)" severity warning;
    end if;
  end process;
end test;

entity vlsi_1 is
  port(
    b2, b1, a2, a1, x : in  bit;
    d4, d3, d2, d1    : out bit);
end vlsi_scas;
 
architecture DNF of vlsi_1 is
begin
 
  d4<=
    (b2 and b1 and a2 and a1 and x);
  d3<=
    (b2 and not b1 and a2)
    or(b2 and a2 and not a1)
    or(b2 and b1 and a1 and not x)
    or(b1 and a2 and a1 and not x);
  d2 <=
    (b2 and not a2 and a1 and x)
    or(b1 and a2 and not a1 and x)
    or(b2 and not a2 and not a1 and not x)
    or(not b2 and a2 and not a1 and not x)
    or(not b2 and not b1 and a2 and not x)
    or(not b2 and b1 and a2 and x)
    or(b2 and not b1 and a1 and x)
    or(b2 and not b1 and not a2 and a1)
    or(b2 and b1 and a2 and a1 and not x)
    or(not b2 and b1 and not a2 and a1 and not x);
  d1 <=
    (b1 and a1 and x)
    or(not b1 and a1 and not x)
    or(b1 and not a1 and not x);
end DNF;

entity VLSI_1 is
  port (a2, a1, b2, b1, x : in  bit;
        d4, d3, d2, d1    : out bit);
end VLSI_1;
 
architecture structure of vlsi_1 is
 
  component
    adder_2
    port (a1, b1, a2, b2 : in  bit;
          c2, s2, s1     : out bit);
  end component;
  component mult_2
    port(s1, s0, r1, r0 : in  bit;
         t3, t2, t1, t0 : out bit);
  end component;
  component dd
    port (x1, x2, x3, x4, x5, x6 : in  bit;
          y1, y2, y3             : out bit);
  end component;
  component YY
    port(a2, a1, b2, b1, x       : in  bit;
          f6, f5, f4, f3, f2, f1 : out bit);
  end component;
  signal f1, f2, f3, f4, f5, f6, t4, t3, t2, t1, c2, s2, s1 : bit;
begin
  circ1 : YY
    port map (a2, a1, b2, b1, x, f6, f5, f4, f3, f2, f1);
  circ2 : mult_2
    port map (f2, f1, b2, b1, d4, t3, t2, t1);
  circ3 : adder_2
    port map (f4, f3, f6, f5, c2, s2, s1);
  circ4 : dd
    port map (s1, t1, s2, t2, c2, t3, d1, d2, d3);
 
end structure;
 
entity dd is
  port (x1, x2, x3, x4, x5, x6 : in  bit;
        y1, y2, y3             : out bit);
end dd;
architecture struct_1 of dd is
begin
  y1 <= x1 or x2;
  y2 <= x3 or x4;
  y3 <= x5 or x6;
end struct_1;
 
entity YY is
  port (a2, a1, b2, b1, x      : in  bit;
        f6, f5, f4, f3, f2, f1 : out bit);
end YY;
architecture struct_1 of YY is
begin
  f1 <= x and a1;
  f2 <= x and a2;
  f3 <= not x and a1;
  f4 <= not x and a2;
  f5 <= not x and b1;
  f6 <= not x and b2;
end struct_1;

entity VLSI_1 is
  port (a2, a1, b2, b1, x : in  bit;
        d4, d3, d2, d1    : out bit);
end VLSI_1;
 
architecture str of vlsi_1 is
 
  component
    adder_2
    port (a1, b1, a2, b2 : in  bit;
          c2, s2, s1     : out bit);
  end component;
  component mult_2
    port(s1, s0, r1, r0 : in  bit;
         t3, t2, t1, t0 : out bit);
  end component;
  component YY_MUX
    port (t4, t3, t2, t1, c2, s2, s1, x : in  bit;
          d4, d3, d2, d1                : out bit);
  end component;
 
  signal t4, t3, t2, t1, c2, s2, s1 : bit;
 
begin
  circ1 : YY_MUX port map (t4, t3, t2, t1, c2, s2, s1, x,
                          d4, d3, d2, d1); 
  circ2 : mult_2
    port map (a1, b1, a2, b2, t4, t3, t2, t1);
  circ3 : adder_2
    port map (a1, b1, a2, b2, c2, s2, s1);
end str;
 
entity YY_MUX is
  port (t4, t3, t2, t1, c2, s2, s1, x : in  bit;
        d4, d3, d2, d1                : out bit);
end YY_MUX;
architecture beh of YY_MUX is
begin
  d1 <= (not x and s1) or (x and t1);
  d2 <= (not x and s2) or (x and t2);
  d3 <= (not x and c2) or (x and t3);
  d4 <= x and t4;
end beh;

наверх

4.10.4. Использование “черных ящиков”

entity add2 is
  port (c1, a1, a2 : in  bit;
        c2, s2     : out bit);
end add2;
architecture struct_1 of add2 is
begin
  s2 <= ((not c1) and (not a1) and a2) or
        ((not c1) and a1 and (not a2)) or
        (c1 and (not a1)and (not a2)) or
        (a1 and a2 and c1);
  c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1;

library exemplar;
use exemplar.exemplar_1164.all;
entity circ1_noopt is
  port (x1, x2, x3, clk : in  bit;
        c_q, s1         : out bit);
end circ1_noopt;
 
architecture str of circ1_noopt is
  component
    add2
    port (c1, a1, a2 : in  bit;
          c2, s2     : out bit);
  end component;
  component dlatch
    port(
      d, clk : in  bit;
      q      : out bit);
  end component;
  attribute noopt           : boolean;
  attribute noopt of dlatch : component is true;
  signal c1                 : bit;
begin
  noopt : add2
    port map (c1 => x1, a1 => x2, a2 => x3, s2 => s1, c2 => c1);
  mm2 : dlatch
    port map (d => c1, clk => clk, q => c_q);
end str;

entity dlatch is
  port(
    d, clk : in  bit;
    q      : out bit);
end dlatch;
 
architecture functional of dlatch is
begin
  dff : process
  begin
    wait until clk'event and clk = '1';
    Q <= D;
  end process;
end functional;

# Reading D:/Modeltech_6.1b/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.1b Sep  8 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "D:/word/VHDL_:=838/COD/VHDL_2002_SINTEZ/P_4_10_4/circ1_noopt.vhd"

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4.11. Повторный синтез

entity minim1 is
  port(
    x1, x2, x3 : in  bit;
    y1         : out bit);
end minim1;
 
architecture beh of minim1 is
-- функциональное описание
begin
  y1 <= (not x1 and not x2 and not x3) or
        (not x1 and not x2 and x3) or (x1 and not x2 and not x3) or
        (not x1 and x2 and not x3) or (x1 and x2 and not x3);
end beh;

entity minim1 is
  port(
    x1, x2, x3 : in  bit;
    y1         : out bit);
end minim1;
 
architecture str of minim1 is
  component and_3
    port (x1, x2, x3 : in  bit;
          y          : out bit);
  end component;
  component or_5
    port (x1, x2, x3, x4, x5 : in  bit;
          y                  : out bit);
  end component;
  component inv
    port (x1 : in  bit;
          y  : out bit);
  end component;
  signal w1, w2, w3, z1, z2, z3, z4, z5 : bit;
-- структурное описание
begin
  p1 : inv port map (x1, w1);
  p2 : inv port map (x2, w2);
  p3 : inv port map (x3, w3);
  p4 : and_3 port map (w1, w2, w3, z1);
  p5 : and_3 port map (w1, w2, x3, z2);
  p6 : and_3 port map (x1, w2, w3, z3);
  p7 : and_3 port map (w1, x2, w3, z4);
  p8 : and_3 port map (x1, x2, x3, z5);
  p9 : or_5 port map (z1, z2, z3, z4, z5, y1);
end str;
 
entity and_3 is
  port (x1, x2, x3 : in bit; y : out bit);
end and_3;
architecture beh of and_3 is
begin
  y <= x1 and x2 and x3;
end beh;
 
entity or_5 is
  port (x1, x2, x3, x4, x5 : in bit; y : out bit);
end or_5;
architecture beh of or_5 is
begin
  y <= x1 or x2 or x3 or x4 or x5;
end beh;
 
entity inv is
  port (x1 : in bit; y : out bit);
end inv;
architecture beh of inv is
begin
  y <= not x1;
end beh;

entity resinthesis is
  port(
    x1, x2, x3, clk : in  bit;
    y               : out bit);
end resinthesis;
 
architecture beh of resinthesis is
  component dlatch
    port(
      d, clk : in  bit;
      q      : out bit);
  end component;
 
  attribute noopt           : boolean;
  attribute noopt of dlatch : component is true;
 
  signal w1, w2, w3, w4, w5, f : bit;
begin
 
  w1 <= (not x1 and x2) or (x1 and not x2);
  w2 <= (not x3 and w1) or (x3 and not w1);
  w3 <= not w2;
  w4 <= w3 and x1;
  w5 <= w2 and x3;
  f  <= w4 or w5;
  p0 : dlatch port map (f, clk, y);
end beh;

entity sovmest_1 is
  port(
    x1, x2, x3, x4, x5 : in  bit;
    y1, y2, y3         : out bit);