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Содержание:
Глава 1. Основные элементы языка VHDL
1.1. Структурное и поведенческое описание цифровой системы
1.2. Лексические элементы и типы данных
1.3. Декларации
1.4. Интерфейс и архитектура объекта
1.5. Атрибуты
1.6. Имена
1.7. Операторы
1.8. Понятие сигнала в языке VHDL
1.9. Дельта-задержка
Упражнения
Глава 2. Последовательные и параллельные операторы
2.1. Последовательные операторы
2.2. Параллельные операторы
Упражнения
Глава 3. Организация проекта
3.1. Подпрограммы
3.2. Функции
3.3. Процедуры
3.4. Разрешающие функции. Пакет std_logic_1164
3.5. Архитектура
3.6. Декларация интерфейса объекта
3.7. Карта портов и карта настройки
3.8. Конфигурация
3.9. Блоки проекта и VHDL-библиотеки
Упражнения
Глава 4. Примеры проектирования на VHDL
4.1. Стили описания поведения
4.2. Формы описания сигналов
4.3. Описание автоматов
4.4. Отладка VHDL-описаний
4.5. Синтезируемое подмножество языка VHDL
Упражнения
Литература
Приложения
1. Форма задания синтаксических конструкций языка VHDL
2. Синтаксис языка VHDL’93
3. Пакет STANDARD
4. Пакет STD_LOGIC_1164
наверх
1.1. Структурное и поведенческое описание цифровой системы
entity add1 is
port (b1, b2 : in bit;
c1, s1 : out bit);
end add1;
architecture struct_1 of add1 is
begin
s1 <= ((b1 and (not b2)) or ((not b1) and b2));
c1 <= b1 and b2;
end struct_1; |
entity add2 is
port (c1, a1, a2 : in bit;
c2, s2 : out bit);
end add2;
architecture struct_1 of add2 is
begin
s2 <= ((not c1) and (not a1) and a2) or
((not c1) and a1 and (not a2)) or
(c1 and (not a1)and (not a2)) or
(a1 and a2 and c1);
c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1; |
entity adder_2 is
port (a1, b1, a2, b2 : in bit;
c2, s2, s1 : out bit);
end adder_2;
architecture structure of adder_2 is
component
add1
port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
component add2
port(c1, a1, a2 : in bit;
c2, s2 : out bit);
end component;
signal c1 : bit;
begin
circ1 : add1
port map (b1, b2, c1, s1);
circ2 : add2
port map (c1, a1, a2, c2, s2);
end structure; |
entity and2 is -- декларация имени объекта проекта
port (x1, x2 : in bit; -- декларация входных портов
y : out bit); -- декларация выходного порта
end and2;
architecture functional of and2 is -- декларация архитектуры
begin
y <= x1 and x2; -- описание функции объекта
end functional; |
entity dd is
port (x1, x2, x3, x4, x5, x6 : in bit;
y1, y2, y3 : out bit);
end dd;
architecture struct_1 of dd is
begin
y1 <= x1 or x2;
y2 <= x3 or x4;
y3 <= x5 or x6;
end struct_1; |
entity mult_2 is
port (s1, s0, r1, r0 : in bit;
t3, t2, t1, t0 : out bit);
end mult_2;
architecture structure of mult_2 is
component
add1 port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
signal p1, p2, p3, p4 : bit;
begin
t0 <= r0 and s0; -- элемент el_1
p2 <= r0 and s1; -- элемент el_3
p1 <= r1 and s0; -- элемент el_2
p4 <= r1 and s1; -- элемент el_4
circ1 : add1 port map (p1, p2, p3, t1);
circ2 : add1 port map (p3, p4, t3, t2);
end structure; |
entity Test_add1 is
end Test_add1;
architecture Behavior of test_add1 is
component add1
port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
signal b1, b2 : bit;
signal c1, s1 : bit;
begin
p1 : add1 port map (b1 => b1, b2 => b2, c1 => c1, s1 => s1);
b2 <= '1',
'0' after 50 ns,
'1' after 100 ns,
'0' after 150 ns,
'1' after 200 ns;
b2 <= '1',
'1' after 50 ns,
'1' after 100 ns,
'0' after 150 ns,
'0' after 200 ns,
'1' after 250 ns;
end behavior; |
entity vlsi_1 is
port (a, b : in integer range 0 to 3;
x : in bit;
D : out integer range 0 to 15);
end vlsi_1;
architecture functional of vlsi_1 is
signal e : integer range 0 to 15;
begin
p0 : process(a, b, x)
begin
if (x = '0') then
e <= a + b;
elsif (x = '1') then
e <= a * b;
end if;
end process;
D <= e;
end functional; |
entity vlsi_1 is
port (a2, a1, b2, b1, x : in bit;
d4, d3, d2, d1 : out bit);
end vlsi_1;
architecture structure of vlsi_1 is
component adder_2 -- декларация компонента
port (a1, b1, a2, b2 : in bit;
c2, s2, s1 : out bit);
end component;
component mult_2 -- декларация компонента
port(s1, s0, r1, r0 : in bit;
t3, t2, t1, t0 : out bit);
end component;
component dd -- декларация компонента
port (x1, x2, x3, x4, x5, x6 : in bit;
y1, y2, y3 : out bit);
end component;
component yy -- декларация компонента
port(a2, a1, b2, b1, x : in bit;
f6, f5, f4, f3, f2, f1 : out bit);
end component;
signal f1, f2, f3, f4, f5, f6, t4, t3, t2, t1, c2, s2, s1 : bit;
-- декларация внутренних сигналов
begin
circ1 : yy
port map (a2, a1, b2, b1, x, f6, f5, f4, f3, f2, f1);
circ2 : mult_2
port map (f2, f1, b2, b1, d4, t3, t2, t1);
circ3 : adder_2
port map (f4, f3, f6, f5, c2, s2, s1);
circ4 : dd
port map (s1, t1, s2, t2, c2, t3, d1, d2, d3);
end structure; |
entity YY is
port (a2, a1, b2, b1, x : in bit;
f6, f5, f4, f3, f2, f1 : out bit);
end YY;
architecture struct_1 of YY is
begin
f1 <= x and a1;
f2 <= x and a2;
f3 <= not x and a1;
f4 <= not x and a2;
f5 <= not x and b1;
f6 <= not x and b2;
end struct_1; |
наверх
1.2. Лексические элементы и типы данных
package multiplexer is
procedure MX(
signal SEL : in bit;
signal x0 : in bit;
signal x1 : in bit;
signal F : out bit);
end multiplexer;
package body multiplexer is
procedure MX(
signal SEL : in bit;
signal x0 : in bit;
signal x1 : in bit;
signal F : out bit) is
begin
case SEL is
when '0' => F <= x0;
when others => F <= x1;
end case;
end MX;
end multiplexer; |
наверх
1.4. Интерфейс и архитектура объекта
entity ANDOR is
port (x1, x2, x3 : in bit;
f : out bit);
end ANDOR;
architecture RTL1 of ANDOR is
begin
f <= (x1 and x2) or x3;
end RTL1;
architecture RTL2 of ANDOR is
signal w : bit;
begin
w <= x1 and x2;
p1 : process (w, x3)
begin
f <= w or x3;
end process p1;
end RTL2; |
наверх
1.5. Атрибуты
entity signal_ex is
end signal_ex;
architecture beh of signal_ex is
signal ex, y1, y3 : bit;
signal y2 : boolean;
begin
ex <= '0' after 20 ns,
'1' after 50 ns,
'0' after 60 ns,
'1' after 80 ns;
y1 <= ex'transaction; y2 <= ex'event; y3 <= ex'last_value;
end beh; |
entity test_attr_scalar is
end test_attr_scalar;
architecture beh of test_attr_scalar is
type new_values is (a1, b1, a2, b2, a3, b3, w);
signal A, B, C, D : new_values;
signal H : integer;
signal K, L, M, N, P : new_values;
begin
A <= new_values'left;
B <= new_values'right;
C <= new_values'low;
D <= new_values'high;
H <= new_values'pos(b3);
K <= new_values'val(2);
-- L <= new_values'succ(w); -- bad
L <= new_values'succ(b3);
M <= new_values'pred(b2);
-- N <= new_values'leftof(a1); -- bad
N <= new_values'leftof(b1);
-- P <= new_values'rightof(w); -- bad
P <= new_values'rightof(b3);
end beh; |
entity test_attr_vector is
end test_attr_vector;
architecture beh of test_attr_vector is
type vector is array (7 downto 0) of bit;
signal x : vector;
signal A, B, C, D : integer;
signal E : boolean;
signal F, G, H : integer;
begin
A <= vector'left;
B <= vector'right;
C <= vector'low;
D <= vector'high;
F <= vector'range;
G <= vector'reverse_range;
H <= vector'length; end beh; |
наверх
1.8. Понятие сигнала в языке VHDL
entity ANDOR is
port(x1, x2, x3 : in bit;
f : out bit);
end ANDOR;
architecture example of ANDOR is
signal w : bit;
begin
p0 : w <= x1 and x2 after 10 ns;
p1 : process (w, x3)
begin
f <= w or x3 after 20 ns;
end process p1;
end example; |
наверх
1.9. Дельта-задержка
entity ANDOR is
port(x1, x2, x3 : in bit;
f : out bit);
end ANDOR;
architecture DELTA of ANDOR is
signal w : bit;
begin
p0 : w <= x1 and x2; -- нет слова after
p1 : process(w, x3)
begin
f <=w or x3; -- нет слова after
end process p1;
end DELTA; |
наверх
Упражнения (глава 1)
entity EXP is
end EXP;
architecture RTL of EXP is
signal A, B, C, D, E, F : bit;
signal X, Y, Z, S, T, R : bit;
begin
R <= A and B and C;
S <= B or C or D;
T <= A and B or D;
Y <= C nor E nor F;
X <= A and not B and not C;
Z <= F nand E nand B;
end RTL; |
наверх
2.1. Последовательные операторы
entity CALL_PRO is
end CALL_PRO;
architecture RTL of CALL_PRO is
function bit_bool (inp_bit : in bit) return boolean is
begin
if (inp_bit = '1') then
return true;
else
return false;
end if;
end bit_bool;
procedure left_one (
signal DATA : in bit_vector (1 to 8);
signal l_bit : out integer) is
variable temp : integer;
begin
temp := 0;
for i in 1 to 8 loop
if (DATA(i) = '1') then
temp := i;
end if;
if (temp /= 0) then exit;
end if;
end loop;
l_bit <= temp;
end left_one;
signal DIN : bit_vector (1 to 8);
signal bit_1 : bit;
signal bool_1 : boolean;
signal DOUT : integer;
begin
p0 : process (bit_1, DIN)
begin
bool_1 <= bit_bool(bit_1); -- вызов функции
LEFT_ONE(DIN, DOUT); -- вызов процедуры
end process;
p1 : process
begin
bit_1 <= '1' after 20 ns, '0' after 40 ns;
DIN <= "01010000" after 20 ns,
"00000000" after 40 ns,
"00001100" after 60 ns,
"00000001" after 80 ns;
wait for 100 ns;
end process;
end RTL; |
use work.PACK.all;
entity CASESTMT is
port (
MONTH : in month_type;
LEAP : in boolean;
DAYS : out integer);
end CASESTMT;
architecture RTL of CASESTMT is
begin
p0 : process (LEAP, MONTH)
begin
case MONTH is
when FEB =>
if LEAP then
DAYS <= 29;
else
DAYS <= 28;
end if;
when APR | JUN | SEP | NOV =>
DAYS <= 30;
when JUL to AUG =>
DAYS <= 31;
when others =>
DAYS <= 31;
end case;
end process;
end RTL; |
entity IFSTMT is
port (
RSTn, CLK, EN, PL : in bit;
DATA : in integer range 0 to 31;
COUNT : out integer range 0 to 31);
end IFSTMT;
architecture RTL of IFSTMT is
signal COUNT_VALUE : integer range 0 to 31;
begin
p0 : process (RSTn, CLK)
begin
if (RSTn = '0') then
COUNT_VALUE <= 0;
elsif (CLK'event and CLK = '1') then
if (PL = '1') then
COUNT_VALUE <= DATA;
elsif (EN = '1') then
if (COUNT_VALUE = 31) then
COUNT_VALUE <= 0;
else
COUNT_VALUE <= COUNT_VALUE + 1;
end if;
end if;
end if;
end process;
COUNT <= COUNT_VALUE;
end RTL; |
package PACK is
type month_type is (JAN, FEB, MAR, APR, MAY, JUN,
JUL, AUG, SEP, OCT, NOV, DEC);
end PACK; |
entity VAR is
end VAR;
architecture functional of VAR is
signal A, B, J : bit_vector(1 downto 0);
signal E, F, G : bit;
begin
p0 : process (A, B, E, F, G, J)
variable C, D, H, Y : bit_vector(1 downto 0);
variable W, Q : bit_vector(3 downto 0);
variable Z : bit_vector(0 to 7);
variable X : bit;
variable DATA : bit_vector(31 downto 0);
begin
C := "11";
X := E and F;
Y := H nand J;
Z(0 to 3) := C & D; -- конкатенация
Z(4 to 7) := (not A) & (A nor B); -- конкатенация
D := ('0', '0'); -- агрегат
W := (2 downto 1 => G, 3 => '1', others => '0'); -- агрегат
DATA := (others => '1'); -- агрегат
end process;
end functional; |
наверх
2.2. Параллельные операторы
entity add1_e is
port (b1, b2, enable : in bit;
c1, s1 : out bit);
end add1_e;
architecture struct_3 of add1_e is
begin
p0 : block (enable = '1')
begin
s1 <= guarded (b1 xor b2);
c1 <= guarded (b1 and b2);
end block p0;
end struct_3; |
entity add1 is
port (b1, b2 : in bit;
c1, s1 : out bit);
end add1;
architecture struct_1 of add1 is
begin
s1 <= ((b1 and (not b2)) or ((not b1) and b2));
c1 <= b1 and b2;
end struct_1; |
entity add2 is
port (c1, a1, a2 : in bit;
c2, s2 : out bit);
end add2;
architecture struct_1 of add2 is
begin
s2 <= ((not c1) and (not a1) and a2) or
((not c1) and a1 and (not a2)) or
(c1 and (not a1)and (not a2)) or
(a1 and a2 and c1);
c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1; |
entity adder_2p is
port (a1, b1, a2, b2, c0 : in bit;
c2, s2, s1 : out bit);
end adder_2p;
architecture structural of adder_2p is
component add2
port(c1, a1, a2 : in bit;
c2, s2 : out bit);
end component;
signal c1 : bit;
begin
circ1 : add2
port map (c1 => c0, a1 => b1, a2 => b2, c2 => c1, s2 => s1);
circ2 : add2
port map (c1 => c1, a1 => a1, a2 => a2, c2 => c2, s2 => s2);
end structural; |
entity adder_N_block is
port (a, b : in bit_vector (0 to 6);
s : out bit_vector (0 to 6);
c : out bit);
end adder_N_block;
architecture structural of adder_N_block is
component add1
port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
component adder_2p
port(a1, b1, a2, b2, c0 : in bit;
c2, s2, s1 : out bit);
end component;
signal c_in : bit_vector (0 to 2);
begin
p0 : add1 port map (b1 => a(0), b2 => b(0),
c1 => c_in(0), s1 => s(0));
block0 : block
begin
stage1 : adder_2p port map (c0 => c_in(0), a1 => a(1), b1 => b(1),
a2 => a(2), b2 => b(2), c2 => c_in(1), s2 => s(2), s1 => s(1));
stage2 : adder_2p port map (c0 => c_in(1), a1 => a(3), b1 => b(3),
a2 => a(4), b2 => b(4), c2 => c_in(2), s2 => s(4), s1 => s(3));
end block;
stage3 : adder_2p port map (c0 => c_in(2), a1 => a(5), b1 => b(5),
a2 => a(6), b2 => b(6), c2 => c, s2 => s(6), s1 => s(5));
end structural; |
entity adder_N_comp is
port (a, b : in bit_vector (0 to 6);
s : out bit_vector (0 to 6);
c : out bit);
end adder_N_comp;
architecture structural of adder_N_comp is
component
add1
port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
component add2
port(c1, a1, a2 : in bit;
c2, s2 : out bit);
end component;
signal c_in : bit_vector (0 to 5);
begin
p0 : add1
port map (b1 => a(0), b2 => b(0), c1 => c_in(0), s1 => s(0));
p1 : add2
port map (c1 => c_in(0), a1 => a(1), a2 => b(1), c2 => c_in(1), s2 => s(1));
p2 : add2
port map (c1 => c_in(1), a1 => a(2), a2 => b(2), c2 => c_in(2), s2 => s(2));
p3 : add2
port map (c1 => c_in(2), a1 => a(3), a2 => b(3), c2 => c_in(3), s2 => s(3));
p4 : add2
port map (c1 => c_in(3), a1 => a(4), a2 => b(4), c2 => c_in(4), s2 => s(4));
p5 : add2
port map (c1 => c_in(4), a1 => a(5), a2 => b(5), c2 => c_in(5), s2 => s(5));
p6 : add2
port map (c1 => c_in(5), a1 => a(6), a2 => b(6), c2 => c, s2 => s(6));
end structural; |
entity adder_N is
generic (N : natural := 4);
port (a, b : in bit_vector (0 to N-1);
s : out bit_vector (0 to N-1);
c : out bit);
end adder_N;
architecture func_1 of adder_N is
component add2
port(c1, a1, a2 : in bit;
c2, s2 : out bit);
end component;
signal c_in : bit_vector (0 to N);
begin -- в схеме (рис. 2.5) все одноразрядные сумматоры - add2
c_in(0) <= '0';
adder : for i in 0 to N-1 generate
i_bit_slice : add2 port map (c1 => c_in(i), a1 => a(i), a2 => b(i),
c2 => c_in(i+1), s2 => s(i));
end generate adder;
c <= c_in(N);
end func_1; |
entity adder_N is
generic (N : natural := 4);
port (a, b : in bit_vector (0 to N-1);
s : out bit_vector (0 to N-1);
c : out bit);
end adder_N;
architecture functional of adder_N is
component
add1
port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
component add2
port(c1, a1, a2 : in bit;
c2, s2 : out bit);
end component;
signal c_in : bit_vector (0 to N-1);
begin
adder : for i in 0 to N-1 generate
first_bit : if (i = 0) generate
first_cell :
add1 port map (b1 => a(0), b2 => b(0),
c1 => c_in(0), s1 => s(0));
end generate first_bit;
middle_bit : if (i > 0) and (i < N-1) generate
middle_cell :
add2 port map (c1 => c_in(i-1), a1 => a(i), a2 => b(i),
c2 => c_in(i), s2 => s(i));
end generate middle_bit;
end_bit : if (i = N-1) generate
end_cell :
add2 port map (c1 => c_in(i-1), a1 => a(i), a2 => b(i),
c2 => c, s2 => s(i));
end generate end_bit;
end generate adder;
end functional; |
entity call_parallel is
port (
data_inp : in bit_vector(5 downto 0);
data_out : out bit_vector(1 downto 0));
end call_parallel;
architecture RTL of call_parallel is
procedure N_XOR (
signal x1, x2, x3 : in bit;
signal f : out bit) is
begin
f <= x1 xor x2 xor x3;
end N_XOR;
begin
N_XOR (x1 => data_inp(5), x2 => data_inp(4), x3 => data_inp(3),
f => data_out(1));
p0 : N_XOR (data_inp(2), data_inp(1), data_inp(0), data_out(0));
end RTL; |
entity DFF is
port (
RSTn, CLK, D : in bit;
Q : out bit);
end DFF;
architecture RTL of DFF is
begin
process (RSTn, CLK)
begin
if (RSTn = '0') then
Q <= '0';
elsif (CLK'event and CLK = '1') then
Q <= D;
end if;
end process;
end RTL; |
entity dlatch is
port (D, clk, clr : in bit; Q : out bit);
end dlatch;
architecture functional of dlatch is
begin
P : block (clk = '1' or clr = '1')
begin
Q <= guarded '0' when clr = '1' else
D when clk = '1' else
unaffected;
end block P;
end functional; |
entity example_condition is
port (
x1, x2, x3, x4 : in bit;
condition : in bit_vector(1 downto 0);
F : out bit);
end example_condition;
architecture first of example_condition is
begin
F <= x1 when condition = "00" else
x2 when condition = "01" else
x3 when condition = "10" else
x4;
end first;
architecture second of example_condition is
begin
process (x1, x2, x3, x4, condition)
begin
if (condition = "00") then
F <= x1;
elsif (condition = "01") then
F <= x2;
elsif (condition = "10") then
F <= x3;
else
F <= x4;
end if;
end process;
end second; |
entity example_selection is
port (x1, x2, x3, x4 : in bit;
selection : in bit_vector(1 downto 0);
F : out bit);
end example_selection;
architecture first of example_selection is
begin
with selection select
F <= x1 when "00",
x2 when "01",
x3 when "10",
x4 when others;
end first;
architecture second of example_selection is
begin
process (x1, x2, x3, x4, selection)
begin
case selection is
when "00" => F <= x1;
when "01" => F <= x2;
when "10" => F <= x3;
when others => F <= x4;
end case;
end process;
end second; |
entity SHIFT is
port (
RSTn, CLK, SI : in bit;
SO : out bit);
end SHIFT;
architecture RTL2 of SHIFT is
component DFF
port (
RSTn, CLK, D : in bit;
Q : out bit);
end component;
signal T : bit_vector(6 downto 0);
begin
g0 : for i in 7 downto 0 generate
g1 : if (i = 7) generate
bit7 : DFF
port map (RSTn => RSTn, CLK => CLK, D => SI, Q => T(6));
end generate;
g2 : if (i > 0) and (i < 7) generate
bitm : DFF
port map (RSTn, CLK, T(i), T(i-1));
end generate;
g3 : if (i = 0) generate
bit0 : DFF
port map (RSTn, CLK, T(0), SO);
end generate;
end generate;
end RTL2; |
entity SHIFT is
port (
RSTn, CLK, SI : in bit;
SO : out bit);
end SHIFT;
architecture RTL3 of SHIFT is
component DFF
port (
RSTn, CLK, D : in bit;
Q : out bit);
end component;
signal T : bit_vector(8 downto 0); -- декларация сигнала T
begin
T(8) <= SI;
SO <= T(0);
g0 : for i in 7 downto 0 generate
allbit : DFF
port map (RSTn => RSTn, CLK => CLK, D => T(i+1), Q => T(i));
end generate;
end RTL3; |
entity SHIFT is
port (
RSTn, CLK, SI : in bit;
SO : out bit);
end SHIFT;
architecture RTL1 of SHIFT is
component DFF
port (
RSTn, CLK, D : in bit;
Q : out bit);
end component;
signal T : bit_vector(6 downto 0);
begin
bit7 : DFF
port map (RSTn => RSTn, CLK => CLK, D => SI, Q => T(6));
bit6 : DFF
port map (RSTn, CLK, T(6), T(5));
bit5 : DFF
port map (RSTn, CLK, T(5), T(4));
bit4 : DFF
port map (CLK => CLK, RSTn => RSTn, D => T(4), Q => T(3));
bit3 : DFF
port map (RSTn, CLK, T(3), T(2));
bit2 : DFF
port map (RSTn, CLK, T(2), T(1));
bit1 : DFF
port map (RSTn, CLK, T(1), T(0));
bit0 : DFF
port map (RSTn, CLK, T(0), SO);
end RTL1; |
наверх
Упражнения (глава 2)
entity IFCASE is
port (
HEX : in bit_vector(3 downto 0);
LED : out bit_vector(6 downto 0));
end IFCASE;
architecture RTL of IFCASE is
begin
p0 : process (HEX)
begin
case HEX is
when "0000" => LED <= "1111110";
when "0001" => LED <= "1100000";
when "0010" => LED <= "1011011";
when "0011" => LED <= "1110011";
when "0100" => LED <= "1100101";
when "0101" => LED <= "0110111";
when "0110" => LED <= "0111111";
when "0111" => LED <= "1100010";
when "1000" => LED <= "1111111";
when "1001" => LED <= "1110111";
when "1010" => LED <= "0111001";
when "1011" => LED <= "0111101";
when "1100" => LED <= "0011001";
when "1101" => LED <= "1111001";
when "1110" => LED <= "1011111";
when others => LED <= "0001111";
end case;
end process;
end RTL; |
entity PROCALL_EX is
end PROCALL_EX;
architecture RTL of PROCALL_EX is
procedure ANDOR (
signal A, B, C, D : in bit_vector(1 downto 0);
signal Y : out bit_vector(1 downto 0)) is
begin
Y <= (A and B) or (C and D);
end ANDOR; signal DIN, DOUT : bit_vector(7 downto 0);
signal X, Y, Z : bit_vector(1 downto 0);
begin
call0 : ANDOR (A => DIN(7) & DIN(6), B => DIN(5 downto 4),
C => DIN(3 downto 2), D => DIN(1 downto 0),
Y => DOUT(1 downto 0));
call1 : ANDOR (A => DIN(7 downto 6), B => DIN(5 downto 4),
C => DIN(3 downto 2), D => DIN(1 downto 0),
Y => DOUT(3 downto 2));
call2 : ANDOR (A => DIN(7 downto 6) and DIN(5 downto 4),
B => DIN(5 downto 4),
C => DIN(3 downto 2), D => DIN(1 downto 0),
Y => DOUT(5 downto 4));
call3 : ANDOR (A => X nand Y, B => Z,
C => DIN(3 downto 2), D => DIN(1 downto 0),
Y => DOUT(7 downto 6));
end RTL; |
наверх
3.4. Разрешающие функции. Пакет std_logic_1164
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.wire.all;
entity circuit_wire is
port (x1, x2, x3, x4, x5, x6 : in std_logic;
out_circ : out std_logic);
end circuit_wire;
architecture structure of circuit_wire is
component cc
port (x1, x2 : in std_logic; y : out std_logic);
end component;
signal out_wire : resolved_bit;
begin
p1 : cc
port map (x1 => x1, x2 => x2, y => out_wire);
p2 : cc
port map (x1 => x3, x2 => x4, y => out_wire);
p3 : cc
port map (x1 => x5, x2 => x6, y => out_wire);
p4 : cc
port map (x1 => out_wire, x2 => x2, y => out_circ);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity cc is -- описание логического элемента И
port (x1, x2 : in std_logic;
y : out std_logic);
end cc;
architecture functional of cc is
begin
y <= x1 and x2;
end functional; |
library IEEE;
use IEEE.std_logic_1164.all;
package wire is
function RES_FUNC(DATA : in std_logic_vector) return std_logic;
subtype RESOLVED_BIT is RES_FUNC std_logic;
end;
package body wire is
-- описание разрешающей функции
function RES_FUNC(DATA : in std_logic_vector) return std_logic is
begin
for I in DATA'range loop
if DATA(I) = '1' then
return '1';
end if;
end loop;
return '0';
end;
end; |
наверх
3.6. Декларация интерфейса объекта
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is -- D-триггер
generic (
PRESET_CLRn : in integer);
port (
RSTn, CLK, D : in std_logic;
Q : out std_logic);
end DFF;
architecture RTL of DFF is
begin
process (RSTn, CLK)
begin
if (RSTn = '0') then
if (PRESET_CLRn = 0) then
Q <= '0';
else
Q <= '1';
end if;
elsif (CLK'event and CLK = '1') then
Q <= D;
end if;
end process;
end RTL; |
library IEEE;
use IEEE.std_logic_1164.all;
entity SHIFTN is -- сдвиговый регистр длины N
generic (
PRESET_CLRn : in integer;
N : in integer);
port (
RSTn, CLK, SI : in std_logic;
SO : out std_logic);
signal T : std_logic_vector(N downto 0);
begin
assert (N > 3) and (N < 33) report
"N outside of range 3 to 32";
end SHIFTN;
architecture RTL1 of SHIFTN is
component DFF
generic (
PRESET_CLRn : in integer);
port (
RSTn, CLK, D : in std_logic;
Q : out std_logic);
end component;
begin
T(N) <= SI;
SO <= T(0);
g0 : for i in N-1 downto 0 generate
allbit : DFF
generic map (PRESET_CLRn => PRESET_CLRn)
port map (RSTn => RSTn, CLK => CLK, D => T(i+1), Q => T(i));
end generate;
end RTL1; |
наверх
3.8. Конфигурация
entity add1 is
port (b1, b2 : in bit;
c1, s1 : out bit);
end add1;
architecture struct_1 of add1 is
begin
s1 <= ((b1 and (not b2)) or ((not b1) and b2));
c1 <= b1 and b2;
end struct_1; |
entity add2 is
port (c1, a1, a2 : in bit;
c2, s2 : out bit);
end add2;
architecture struct_1 of add2 is
begin
s2 <= ((not c1) and (not a1) and a2) or
((not c1) and a1 and (not a2)) or
(c1 and (not a1)and (not a2)) or
(a1 and a2 and c1);
c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1; |
entity adder_2 is
port (a1, b1, a2, b2 : in bit;
c2, s2, s1 : out bit);
end adder_2;
architecture structure of adder_2 is
component
add1
port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
component add2
port(c1, a1, a2 : in bit;
c2, s2 : out bit);
end component;
signal c1 : bit;
begin
circ1 : add1
port map (b1, b2, c1, s1);
circ2 : add2
port map (c1, a1, a2, c2, s2);
end structure; |
entity and2 is -- декларация имени объекта проекта
port (x1, x2 : in bit; -- декларация входных портов
y : out bit); -- декларация выходного порта
end and2;
architecture functional of and2 is -- декларация архитектуры
begin
y <= x1 and x2; -- описание функции объекта
end functional; |
configuration bird of flock is -- bird - имя конфигурации
for three_geese
for one : goose
use entity work.goose(struct_2);
end for;
for two : goose
use entity work.goose(struct_1);
end for;
for three : goose
use entity work.goose(struct_1);
end for;
end for;
end bird; |
configuration example of vlsi_1 is
for structure -- имя архитектурного тела схемы vlsi_1
for circ2 : mult_2
use entity work.mult_2(structure);
for structure
for all : add1
use entity work.add1(struct_2);
end for;
end for;
end for;
for circ3 : adder_2
use entity work.adder_2(structure);
for structure
for all : add1
use entity work.add1(struct_1);
end for;
for all : add2
use entity work.add2(struct_1); -- вместо struct_1
end for; -- можно указать
end for; -- другую архитектуру
end for;
end for;
end example; |
entity flock is
port (a, b : bit; c : out bit);
end flock;
architecture three_geese of flock is
signal w, r : bit;
component goose -- декларация компонента
port (a, b : bit; c : out bit);
end component;
begin
one : goose port map (a, b, w);
-- создание экземпляра компонента
two : goose port map (a, w, r);
three : goose port map (a, r, c);
end three_geese; |
entity goose is
port (a, b : in bit; c : out bit);
end goose;
architecture struct_1 of goose is
begin
c <= a xor b;
end struct_1; |
entity mult_2 is
port (s1, s0, r1, r0 : in bit;
t3, t2, t1, t0 : out bit);
end mult_2;
architecture structure of mult_2 is
component
add1 port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
signal p1, p2, p3, p4 : bit;
begin
t0 <= r0 and s0; -- элемент el_1
p2 <= r0 and s1; -- элемент el_3
p1 <= r1 and s0; -- элемент el_2
p4 <= r1 and s1; -- элемент el_4
circ1 : add1 port map (p1, p2, p3, t1);
circ2 : add1 port map (p3, p4, t3, t2);
end structure; |
entity vlsi_1 is
port (a2, a1, b2, b1, x : in bit;
d4, d3, d2, d1 : out bit);
end vlsi_1;
architecture structure of vlsi_1 is
component adder_2 -- декларация компонента
port (a1, b1, a2, b2 : in bit;
c2, s2, s1 : out bit);
end component;
component mult_2 -- декларация компонента
port(s1, s0, r1, r0 : in bit;
t3, t2, t1, t0 : out bit);
end component;
component dd -- декларация компонента
port (x1, x2, x3, x4, x5, x6 : in bit;
y1, y2, y3 : out bit);
end component;
component yy -- декларация компонента
port(a2, a1, b2, b1, x : in bit;
f6, f5, f4, f3, f2, f1 : out bit);
end component;
signal f1, f2, f3, f4, f5, f6, t4, t3, t2, t1, c2, s2, s1 : bit;
-- декларация внутренних сигналов
begin
circ1 : yy
port map (a2, a1, b2, b1, x, f6, f5, f4, f3, f2, f1);
circ2 : mult_2
port map (f2, f1, b2, b1, d4, t3, t2, t1);
circ3 : adder_2
port map (f4, f3, f6, f5, c2, s2, s1);
circ4 : dd
port map (s1, t1, s2, t2, c2, t3, d1, d2, d3);
end structure; |
entity YY is
port (a2, a1, b2, b1, x : in bit;
f6, f5, f4, f3, f2, f1 : out bit);
end YY;
architecture struct_1 of YY is
begin
f1 <= x and a1;
f2 <= x and a2;
f3 <= not x and a1;
f4 <= not x and a2;
f5 <= not x and b1;
f6 <= not x and b2;
end struct_1; |
наверх
3.9. Блоки проекта и VHDL-библиотеки
library IEEE;
use IEEE.STD_LOGIC_1164. all;
library exemplar;
use exemplar.exemplar_1164.all;
entity shift_example is
port (a, b : in std_logic_vector (3 downto 0);
x1, x2 : out std_logic_vector (3 downto 0));
end shift_example;
architecture Synt of shift_example is
signal y, z : std_logic_vector (3 downto 0);
begin
y <= sl (a, 3); -- сдвиг влево
z <= sr (a, 3); -- сдвиг вправо
x1 <= y and b;
x2 <= z xor b;
end Synt; |
наверх
4.1. Стили описания поведения
entity and_GATE is
port (A, B : in bit;
D : out bit);
end;
architecture beh of and_GATE is
begin
D <= A and B;
end beh; |
entity Decoder is
port (X : in bit_vector (0 to 1);
Y : out bit_vector (0 to 3));
end Decoder;
architecture Data_flow of Decoder is
begin
y(0) <= not x(0) and not x(1);
y(1) <= not x(0) and x(1);
y(2) <= x(0) and not x(1);
y(3) <= x(0) and x(1);
end Data_flow; |
entity Decoder is
port (X : in bit_vector (0 to 1);
Y : out bit_vector (0 to 3));
end Decoder;
architecture Mixed of Decoder is
component Inverter port (A : in bit; B : out bit);
end component;
signal S : bit_vector (0 to 1);
begin
Inv1 : Inverter port map (A => x(0), B => s(0));
Inv2 : Inverter port map (A => x(1), B => s(1));
p : process (s, x)
begin
y(0) <= s(0) and s(1);
y(1) <= s(0) and x(1);
y(2) <= x(0) and s(1);
y(3) <= x(0) and x(1);
end process;
end Mixed; |
entity Decoder is
port (X : in bit_vector (0 to 1);
Y : out bit_vector (0 to 3));
end Decoder;
architecture Procedural of Decoder is
signal s : bit_vector (0 to 3);
begin
process (x, s)
begin
case x is
when "00" => s <= "1000";
when "01" => s <= "0100";
when "10" => s <= "0010";
when "11" => s <= "0001";
end case;
end process;
y <= s;
end Procedural; |
entity Decoder is
port (X : in bit_vector (0 to 1);
Y : out bit_vector (0 to 3));
end Decoder;
architecture structure of Decoder is
signal S : bit_vector (0 to 1);
component AND_Gate port (A, B : in bit; D : out bit);
end component;
component Inverter port (A : in bit; B : out bit);
end component;
begin
Inv1 : Inverter port map (A => x(0), B => s(0));
Inv2 : Inverter port map (A => x(1), B => s(1));
A1 : AND_Gate port map (A => s(0), B => s(1), D => y(0));
A2 : AND_Gate port map (A => s(0), B => x(1), D => y(1));
A3 : AND_Gate port map (A => x(0), B => s(1), D => y(2));
A4 : AND_Gate port map (A => x(0), B => x(1), D => y(3));
end structure; |
entity Inverter is
port (A : in bit;
B : out bit);
end;
architecture beh of Inverter is
begin
B <= not A;
end beh; |
entity test_Decoder is
end test_Decoder;
architecture structure of test_Decoder is
signal X : bit_vector (0 to 1);
signal Y : bit_vector (0 to 3);
component Decoder
port (X : in bit_vector (0 to 1);
Y : out bit_vector (0 to 3));
end component;
begin
p : Decoder port map (X, Y);
X <= "00" after 50 ns, "01" after 100 ns,
"10" after 150 ns, "11" after 200 ns;
end structure; |
наверх
4.2. Формы описания сигналов
library work;
use work.vv_vls.all;
entity adder_2 is
port (a1, b1, a2, b2 : in bit;
c2, s2, s1 : out bit);
end adder_2;
architecture functional of adder_2 is -- функциональное описание
-- сумматора
-- use std.vv_vls.all;
signal aa, bb : integer range 0 to 3;
signal cc : integer range 0 to 7;
signal cc_sig : bit_vector (0 to 3);
begin
aa <= bin2_to_int (a1, b1);
bb <= bin2_to_int (a2, b2);
cc <= aa+bb; -- функция сумматора
cc_sig <= int_to_bin4(cc);
s1 <= cc_sig(0); -- формирование выходных сигналов
s2 <= cc_sig(1);
c2 <= cc_sig(2);
end functional; |
library work;
use work.vv_vls.all;
entity mult_2 is
port (s1, s0, r1, r0 : in bit;
t3, t2, t1, t0 : out bit);
end mult_2;
architecture functional of mult_2 is -- функциональное описание
-- use std.vv_vls.all; -- умножителя
signal ss, rr : integer range 0 to 3;
signal tt : integer range 0 to 9;
signal tt_sig : bit_vector (0 to 3);
begin
ss <= bin2_to_int(s1, s0);
rr <= bin2_to_int(r1, r0);
tt <= ss*rr; -- функция умножителя
tt_sig <= int_to_bin4(tt);
t0 <= tt_sig(0); -- формирование выходных сигналов
t1 <= tt_sig(1);
t2 <= tt_sig(2);
t3 <= tt_sig(3);
end functional; |
package vv_vls is
function bin2_to_int (signal w2, w1 : bit)
return integer;
function int_to_bin4
(signal INPUT : integer)
return bit_vector;
end vv_vls;
package body vv_vls is
function bin2_to_int -- функция преобразования битового
(signal w2, w1 : bit) -- вектора в число
return integer is
variable sum : integer := 0;
begin
if w1 = '1' then
sum := 1;
else
sum := 0;
end if;
if w2 = '1' then
sum := sum+2;
else
sum := sum;
end if;
return sum;
end bin2_to_int;
function int_to_bin4 -- функция преобразования числа
(signal INPUT : integer) -- в битовый вектор
return bit_vector is
variable fout : bit_vector(0 to 3);
variable temp_a : integer := 0;
variable temp_b : integer := 0;
begin
temp_a := INPUT;
for i in 3 downto 0 loop
temp_b := temp_a/(2**i);
temp_a := temp_a rem (2**i);
if (temp_b = 1) then
fout(i) := '1';
else
fout(i) := '0';
end if;
end loop;
return fout;
end int_to_bin4;
end vv_vls; |
наверх
4.3. Описание автоматов
architecture circ_feedback of some_entity is
signal b : bit;
function rising_edge (signal s : bit) return boolean is
begin
return s = '1' and s'event;
end;
begin
process (clk, reset)
begin
if reset = '1' then
c <= '0';
elsif rising_edge(clk)
c <= b;
end if;
end process;
process (a, c) -- комбинационный процесс
begin b <= a and c;
end process;
end circ_feedback; |
library work;
use work.vv_vls.all;
entity FSM_A is
port (z : in fsm_in_type;
clk : in bit;
w : out fsm_out_type);
end FSM_A;
architecture rtl_a of fsm_a is
type T_state is (a1, a2, a3, a4);
signal NEXT_state : T_state;
signal state : T_state;
begin
ns : process (state, z)
begin
case state is
when a1 =>
if (z = z1) then NEXT_state <= a2; w <= w1;
elsif (z = z2) then NEXT_state <= a4; w <= w5;
end if;
when a2 =>
if (z = z1) then NEXT_state <= a2; w <= w1;
elsif (z = z2) then NEXT_state <= a3; w <= w3;
end if;
when a3 =>
if (z = z1) then NEXT_state <= a1; w <= w2;
elsif (z = z2) then NEXT_state <= a4; w <= w4;
end if;
when a4 =>
if (z = z1) then NEXT_state <= a1; w <= w4;
elsif (z = z2) then NEXT_state <= a3; w <= w5;
end if;
end case; end process;
REG : process(clk)
begin
if clk = '1' then
state <= NEXT_state;
end if;
end process;
end rtl_a; |
entity Mealy is
port(x : in bit_vector (4 downto 1); clk, rst : in bit;
y :out bit_vector (6 downto 1));
end Mealy;
architecture rtl of Mealy is
type T_state is (a1, a2, a3, a4, a5, a6);
signal NEXT_state, state : T_state;
begin
ns : process (state, x)
begin
case state is
when a1 =>
NEXT_state <= a2; y <= "000101";
-- код y= (y6, y5, y4, y3, y2, y1)
-- код x= (x4, x3, x2, x1)
when a2 =>
if ((x(1) and not x(2) and not x(3)) = '1')
then NEXT_state <= a2; y <= "000000";
elsif (not x(1) = '1')
then NEXT_state <= a5; y <= "000010";
elsif ((x(1) and not x(2) and x(3)) = '1')
then NEXT_state <= a4; y <= "001000";
elsif ((x(1) and x(2)) = '1')
then NEXT_state <= a3; y <= "000110";
end if;
when a3 => NEXT_state <= a4; y <= "001001";
when a4 => if (x(2) = '1')
then NEXT_state <= a6; y <= "010000";
elsif (not x(2) = '1')
then NEXT_state <= a1; y <= "000000";
end if;
when a5 =>
if ((x(1) and x(4)) = '1')
then NEXT_state <= a5; y <= "000000";
elsif (not x(4) = '1')
then NEXT_state <= a4; y <= "001001";
elsif ((not x(1) and x(4)) = '1')
then NEXT_state <= a1; y <= "100000";
end if;
when a6 => NEXT_state <= a1; y <= "100000";
end case;
end process ns;
state <= a1 when rst = '1' else
NEXT_state when clk'event and clk = '1' else state;
end rtl; |
entity Moore is
port(x : in bit_vector (4 downto 1);
clk, rst : in bit;
y :out bit_vector (6 downto 1));
end Moore;
architecture rtl of Moore is
type T_state is (a1, a2, a3, a4, a5, a6, a7, a8);
signal NEXT_state, state : T_state;
begin
ns : process (state, x)
begin
case state is
when a1 => NEXT_state <= a2;
when a2 =>
if ((x(1) and not x(2) and not x(3)) = '1')
then NEXT_state <= a2;
elsif ((x(1) and x(2)) = '1')
then NEXT_state <= a3;
elsif ((x(1) and not x(2) and x(3)) = '1')
then NEXT_state <= a4;
elsif (not x(1) = '1')
then NEXT_state <= a6;
end if;
when a3 => NEXT_state <= a5;
when a4 =>
if (not x(2) = '1') then NEXT_state <= a1;
elsif (x(2) = '1')
then NEXT_state <= a7;
end if;
when a5 =>
if (not x(2) = '1') then NEXT_state <= a1;
elsif (x(2) = '1') then NEXT_state <= a7;
end if;
when a6 =>
if (not x(4) = '1') then NEXT_state <= a5;
elsif ((x(1) and x(4)) = '1')
then NEXT_state <= a6;
elsif ((not x(1) and x(4)) = '1')
then NEXT_state <= a8;
end if;
when a7 => NEXT_state <= a8;
when a8 => NEXT_state <= a1;
end case;
end process ns;
y <= "000000" when state = a1 else
"000101" when state = a2 else
"000110" when state = a3 else
"001000" when state = a4 else
"001001" when state = a5 else
"000010" when state = a6 else
"010000" when state = a7 else
"100000";
state <= a1 when rst = '1' else
NEXT_state when clk'event and clk = '1' else state;
end rtl; |
package vv_vls is
function bin2_to_int (signal w2, w1 : bit)
return integer;
function int_to_bin4
(signal INPUT : integer)
return bit_vector;
type fsm_in_type is (z1, z2);
type fsm_out_type is (w1, w2, w3, w4, w5);
end vv_vls;
package body vv_vls is
function bin2_to_int -- функция преобразования битового
(signal w2, w1 : bit) -- вектора в число
return integer is
variable sum : integer := 0;
begin
if w1 = '1' then
sum := 1;
else
sum := 0;
end if;
if w2 = '1' then
sum := sum+2;
else
sum := sum;
end if;
return sum;
end bin2_to_int;
function int_to_bin4 -- функция преобразования числа
(signal INPUT : integer) -- в битовый вектор
return bit_vector is
variable fout : bit_vector(0 to 3);
variable temp_a : integer := 0;
variable temp_b : integer := 0;
begin
temp_a := INPUT;
for i in 3 downto 0 loop
temp_b := temp_a/(2**i);
temp_a := temp_a rem (2**i);
if (temp_b = 1) then
fout(i) := '1';
else
fout(i) := '0';
end if;
end loop;
return fout;
end int_to_bin4;
end vv_vls; |
наверх
4.4. Отладка VHDL-описаний
entity add1 is
port (b1, b2 : in bit;
c1, s1 : out bit);
end add1;
architecture struct_1 of add1 is
begin
s1 <= ((b1 and (not b2)) or ((not b1) and b2));
c1 <= b1 and b2;
end struct_1; |
entity add2 is
port (c1, a1, a2 : in bit;
c2, s2 : out bit);
end add2;
architecture struct_1 of add2 is
begin
s2 <= ((not c1) and (not a1) and a2) or
((not c1) and a1 and (not a2)) or
(c1 and (not a1)and (not a2)) or
(a1 and a2 and c1);
c2 <= (a1 and c1) or (a2 and c1) or (a1 and a2);
end struct_1; |
entity adder_2 is
port (a1, b1, a2, b2 : in bit;
c2, s2, s1 : out bit);
end adder_2;
architecture structure of adder_2 is
component
add1
port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
component add2
port(c1, a1, a2 : in bit;
c2, s2 : out bit);
end component;
signal c1 : bit;
begin
circ1 : add1
port map (b1, b2, c1, s1);
circ2 : add2
port map (c1, a1, a2, c2, s2);
end structure; |
entity and2 is -- декларация имени объекта проекта
port (x1, x2 : in bit; -- декларация входных портов
y : out bit); -- декларация выходного порта
end and2;
architecture functional of and2 is -- декларация архитектуры
begin
y <= x1 and x2; -- описание функции объекта
end functional; |
entity dd is
port (x1, x2, x3, x4, x5, x6 : in bit;
y1, y2, y3 : out bit);
end dd;
architecture struct_1 of dd is
begin
y1 <= x1 or x2;
y2 <= x3 or x4;
y3 <= x5 or x6;
end struct_1; |
entity mult_2 is
port (s1, s0, r1, r0 : in bit;
t3, t2, t1, t0 : out bit);
end mult_2;
architecture structure of mult_2 is
component
add1 port (b1, b2 : in bit;
c1, s1 : out bit);
end component;
signal p1, p2, p3, p4 : bit;
begin
t0 <= r0 and s0; -- элемент el_1
p2 <= r0 and s1; -- элемент el_3
p1 <= r1 and s0; -- элемент el_2
p4 <= r1 and s1; -- элемент el_4
circ1 : add1 port map (p1, p2, p3, t1);
circ2 : add1 port map (p3, p4, t3, t2);
end structure; |
entity test_vlsi_1 is
end test_vlsi_1;
architecture test of test_vlsi_1 is
component vlsi_1
port (a2, a1, b2, b1, x : in bit;
d4, d3, d2, d1 : out bit);
end component;
signal a2, a1, b2, b1, x, d4, d3, d2, d1 : bit;
begin
p :component vlsi_1
port map (a2 => a2, a1 => a1, b2 => b2, b1 => b1, x => x,
d4 => d4, d3 => d3, d2 => d2, d1 => d1);
b2 <= '1'; b1 <= '1'; a2 <= '1'; a1 <= '0', '1' after 50 ns;
x <= '0', '1' after 30 ns, '0' after 70 ns;
end test; |
entity vlsi_1 is
port (a2, a1, b2, b1, x : in bit;
d4, d3, d2, d1 : out bit);
end vlsi_1;
architecture structure of vlsi_1 is
component adder_2 -- декларация компонента
port (a1, b1, a2, b2 : in bit;
c2, s2, s1 : out bit);
end component;
component mult_2 -- декларация компонента
port(s1, s0, r1, r0 : in bit;
t3, t2, t1, t0 : out bit);
end component;
component dd -- декларация компонента
port (x1, x2, x3, x4, x5, x6 : in bit;
y1, y2, y3 : out bit);
end component;
component yy -- декларация компонента
port(a2, a1, b2, b1, x : in bit;
f6, f5, f4, f3, f2, f1 : out bit);
end component;
signal f1, f2, f3, f4, f5, f6, t4, t3, t2, t1, c2, s2, s1 : bit;
-- декларация внутренних сигналов
begin
circ1 : yy
port map (a2, a1, b2, b1, x, f6, f5, f4, f3, f2, f1);
circ2 : mult_2
port map (f2, f1, b2, b1, d4, t3, t2, t1);
circ3 : adder_2
port map (f4, f3, f6, f5, c2, s2, s1);
circ4 : dd
port map (s1, t1, s2, t2, c2, t3, d1, d2, d3);
end structure; |
entity YY is
port (a2, a1, b2, b1, x : in bit;
f6, f5, f4, f3, f2, f1 : out bit);
end YY;
architecture struct_1 of YY is
begin
f1 <= x and a1;
f2 <= x and a2;
f3 <= not x and a1;
f4 <= not x and a2;
f5 <= not x and b1;
f6 <= not x and b2;
end struct_1; |
наверх
4.5. Синтезируемое подмножество языка VHDL
entity control_case is
port (sel : in bit_vector (0 to 1); a, b, c, d : in bit; m : out bit);
end control_case;
architecture example of control_case is
begin
process (sel, a, b, c, d)
begin
case sel is
when "00" => m <= c;
when "01" => m <= a;
when "10" => m <= d;
when others => m <= b;
end case;
end process;
end example; |
entity control_if is
port (a, b, c : boolean; m : out boolean);
end control_if;
architecture example of control_if is
begin
process (a, b, c)
variable n : boolean;
begin
if a then n := b;
else n := c;
end if;
m <= n;
end process;
end example; |
entity control_loop is
port (a : bit_vector (0 to 3); m : out bit_vector (0 to 3));
end control_loop;
architecture example of control_loop is
begin
process (a)
variable b : bit;
begin
b := '1';
for i in 0 to 3 loop
b := a(3-i) and b;
m(i) <= b;
end loop;
end process;
end example; |
entity logical_ops_2 is
port (a, b : in bit_vector (0 to 3); m : out bit_vector (0 to 3));
end logical_ops_2;
architecture example of logical_ops_2 is
begin
m <= a and b;
end example; |
entity logical_ops_1 is
port (a, b, c, d : in bit; m : out bit);
end logical_ops_1;
architecture example of logical_ops_1 is
signal e : bit;
begin
m <= (a and b) or e; -- оператор назначения сигнала
e <= c xor d;
end example; |
entity relational_ops_2 is
port (a, b : in integer range 0 to 3; m : out boolean);
end relational_ops_2;
architecture example of relational_ops_2 is
begin
m <= a >= b;
end example; |
entity relational_ops_1 is
port (a, b : in bit_vector (0 to 3); m : out boolean);
end relational_ops_1;
architecture example of relational_ops_1 is
begin
m <= a = b;
end example; |
entity subprograms is
port (a : bit_vector (0 to 2); m : out bit_vector (0 to 2));
end subprograms;
architecture example of subprograms is
function simple (w, x, y : bit)
return bit is
begin
return (w and x) or y;
end;
begin
process (a)
begin
m(0) <= simple(a(0), a(1), a(2));
m(1) <= simple(a(2), a(0), a(1));
m(2) <= simple(a(1), a(2), a(0));
end process;
end example; |
library IEEE;
use IEEE.std_logic_1164.all;
entity xor_var is
port (A, B, C : in std_logic;
X, Y : out std_logic);
end xor_var;
architecture example of xor_var is
begin
P : process (A, B, C)
variable W : std_logic;
begin
W := A; X <= C xor W;
W := B; Y <= C xor W;
end process;
end example; |
наверх
Упражнения (глава 4);
entity EX is
port (A : in std_ulogic_vector(0 to 15);
SEL : in integer range 0 to 15;
Z : out std_ulogic);
end EX;
architecture RTL of EX is
begin
WHAT : process (A, SEL)
begin
for I in 0 to 15 loop
if SEL = I then
Z <= A(I);
end if;
end loop;
end process WHAT;
end RTL; |
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