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Оглавление
Предисловие
1. Моделирование и синтез цифровых систем с использованием языка VHDL
1.1. Системы моделирования и синтеза. Использование VHDL-пакетов
1.2. Библиотека синтеза БМК
2. Пакет STANDARD
2.1. Назначение и общая характеристика пакета
2.2. Описание средств пакета
2.3. Синтезируемость конструкций пакета
3. Пакет STD_LOGIC_1164
3.1. Назначение и общая характеристика пакета
3.2. Разрешающие функции
3.3. Многозначный логический тип
3.4. Логические операции и функции
3.5. Кодирование типов данных при синтезе
3.6. Синтезируемость конструкций пакета
3.7. Использование неопределенных состояний don’t care
4. Пакет NUMERIC_STD
4.1. Назначение и общая характеристика пакета
4.2. Функции изменения типа и размерности
4.3. Логические операции
4.4. Операции сдвига и сравнения
4.5. Арифметические операции
4.6. Синтезируемость конструкций пакета
5. Пакет EXEMPLAR_1164
5.1. Назначение и общая характеристика пакета
5.2. Использование атрибутов пакета при синтезе
5.3. Функции и процедуры пакета
5.4. Синтез схем с учетом нагрузочных способностей
6. Моделирование логических схем с использованием пакетов библиотеки VITAL
6.1. Назначение пакетов библиотеки VITAL
6.2. Создание VITAL-библиотеки синтеза
6.3. Синтез логической схемы
6.4. Моделирование логической схемы
7. Пакеты TEXTIO, STD_LOGIC_TEXTIO
7.1. Назначение пакетов
7.2. Типы и процедуры пакетов
7.3. Использование средств пакетов при моделировании
8. Использование VHDL-пакетов в маршруте проектирования БМК
8.1. Пример проектирования арифметико-логического устройства
8.2. Комбинированные маршруты проектирования
8.3. Результаты экспериментов
Список литературы
Приложение 1. Описание библиотеки bmk_little для программы lGen
Приложение 2. VHDL-описания элементов библиотеки bmk_little
1.Файл bmk.vhd, содержащий описания элементов с ненулевыми задержками
2.Файл bmk_pack.vhd, содержащий декларации элементов библиотеки bmk_little
Приложение 3. VITAL-библиотека bmk_little
Файл bmk_VITAL.vhd
Файл bmk_Vcomponents
Файл bmk_Vtables.vhd
Приложение 4. Моделирование схемы АЛУ
1.Структурное описание (netlist) синтезированной схемы alu (файл alu_syn.vhd)
2.SDF-файл синтезированной схемы (alu_syn.sdf)
3.RTL-описание схемы alu после команды unmap (файл alu_RTL.vhd)
наверх
1. Моделирование и синтез цифровых систем с использованием языка VHDL
1.1. Системы моделирования и синтеза. Использование VHDL-пакетов
Листинг 1.1.Пакет wire
package wire is
function RES_FUNC(DATA: in bit_vector) return bit;
subtype RESOLVED_BIT is RES_FUNC bit;
end;
package body wire is
function RES_FUNC(DATA: in bit_vector) return bit is
begin
for I in DATA'range loop
if DATA(I) = '1' then return '1';
end if;
end loop;
return '0';
end;
end; |
1.2. Библиотека синтеза БМК
Листинг 1.2. Описание инвертора для программы lGen
GATE N (
INPUTS A;
OUTPUTS Y;
FUNCTION (Y = !A;);
AREA = 2;
INPUT A (
LIN = 0.022;
DELAY (
PROP = (0.160,0.135);
DRIVE = (2.378,2.009);););
OUTPUT Y (LMAX = 0.3552;);
); |
наверх
3. Пакет STD_LOGIC_1164
3.2. Разрешающие функции
Листинг 3.1.VHDL-описание логической схемы (рис.3.1) с использованием типов bit,resolved_bit
library WORK;
use WORK.wire.all;
entity circuit_wire is
port (
x1, x2, x3, x4, x5, x6 : in bit;
out_circ : out bit);
end circuit_wire;
architecture structure of circuit_wire is
component cc
port (
x1, x2 : in bit;
y : out bit);
end component;
signal out_wire : RESOLVED_BIT;
begin
p1 : cc port map
(x1 => x1, x2 => x2, y => out_wire);
p2 : cc port map
(x1 => x3, x2 => x4, y => out_wire);
p3 : cc port map
(x1 => x5, x2 => x6, y => out_wire);
p4 : cc port map
(x1 => out_wire, x2 => x2, y => out_circ);
end; |
Листинг 3.2.VHDL-описание элемента cc.
entity cc is
port (x1, x2 : in bit;
y : out bit);
end cc;
architecture functional of cc is
begin
y <= x1 and x2;
end functional; |
Листинг 3.3.VHDL-модель секвенциального автомата SEKV
LIBRARY work;
USE work.wire.all;
ENTITY SEKV IS
PORT (CLK, rst, x1, x2 : in bit;
y1, y2 : out RESOLVED_BIT );
END;
ARCHITECTURE BEHAVIOR OF SEKV IS
SIGNAL z0, z1, z2, z3, z4: RESOLVED_BIT := '1';
SIGNAL n_z0, n_z1, n_z2, n_z3, n_z4 : RESOLVED_BIT; SIGNAL n_y1, n_y2 : resolved_bit ;
BEGIN
p1: PROCESS (x1, x2, z0, z1, z2, z3, z4)
BEGIN
n_z0 <= z0; n_z1 <= z1; n_z2 <= z2; n_z3 <= z3;
n_z4 <= z4; n_y1 <= '0'; n_y2 <= '0';
if ( not x1 and x2 and z0 and z1) = '1' then
-- строка 1
n_z0 <= '0'; n_z4 <= '0'; n_y1 <= '1'; n_y2 <= '0';
end if;
if (not x2 and not z0 and z1 and not z4)='1' then
-- строка 2
n_z1 <= '0';n_z2 <= '0';
end if;
if (x2 and z0 and not z1 and not z2) ='1' then
-- строка 3
n_z2 <= '1';
end if;
if (not x1 and not z1 and not z4) = '1' then
-- строка 4
n_z3 <= '0'; n_z4 <= '1'; n_y1 <= '0';
end if;
if (x1 and not z1 and not z4 )='1' then
-- строка 5
n_z3 <= '1'; n_z4 <= '1'; n_y2 <= '1';
end if;
if (not x2 and not z1 and not z3 and z4) = '1' then
-- строка 6
n_z3 <= '1';
end if;
if (z0 and not z1 and z2 and z3 and z4 ) = '1' then
-- строка 7
n_z0 <= '0'; n_z1 <= '1'; n_y2 <= '0';
end if;
if (x1 and not z0 and z1 and z4) = '1' then
-- строка 8
n_z0 <= '1';
end if;
if (not z0 and not z1) = '1' then
-- строка 9
n_z0 <= '1'; n_z2 <= '0'; n_y1 <= '0';
end if;
END PROCESS p1;
p2: PROCESS (CLK, rst)
BEGIN
if (rst = '1') then
y1 <= '0'; y2 <= '0'; -- нач установка
z0 <= '1'; z1 <= '1'; z2 <= '1'; z3 <= '1'; z4 <= '1';
elsif (rst ='0' ) then
if ( CLK='1' AND CLK'event) THEN
y1 <= n_y1; y2 <= n_y2;
z0 <= n_z0; z1 <= n_z1; z2 <= n_z2; z3 <= n_z3;
z4 <= n_z4;
end if;
end if;
END PROCESS p2;
END BEHAVIOR; |
наверх
3.3.Многозначный логический тип
Листинг 3.4.Назначение сигнала FlagC из двух источников
library IEEE;
use IEEE.std_logic_1164.all;
entity test_flag is
end;
architecture beh of test_flag is
signal FlagC : std_logic := 'Z';
signal Carry : boolean;
begin
ALU : process (carry)
begin
if Carry then FlagC <= '1';
end if;
end process ALU;
Comm : process (Carry)
begin
FlagC <= 'Z';
end process Comm;
Carry <= true,
false after 100 ns,
true after 200 ns;
end beh; |
Листинг 3.5.Описание схемы (рис.3.1) с использованием типа std_logic
library IEEE;
use IEEE.std_logic_1164.all;
entity circuit_wire is
port (
x1, x2, x3, x4, x5, x6 : in std_logic;
out_circ : out std_logic);
end circuit_wire;
architecture structure of circuit_wire is
component cc
port (
x1, x2 : in std_logic;
y : out std_logic);
end component;
signal out_wire : std_logic;
begin
p1 : cc port map
(x1 => x1, x2 => x2, y => out_wire);
p2 : cc port map
(x1 => x3, x2 => x4, y => out_wire);
p3 : cc port map
(x1 => x5, x2 => x6, y => out_wire);
p4 : cc port map
(x1 => out_wire, x2 => x2, y => out_circ);
end structure;
-- описание логического элемента И
library IEEE;
use IEEE.std_logic_1164.all;
entity cc is
port ( x1, x2 : in std_logic;
y : out std_logic);
end cc;
architecture functional of cc is
begin
y <= x1 and x2;
end functional; |
Листинг 3.6.Описание схемы (рис.3.1) с использованием собственной разрешающей функции для типа std_logic
library IEEE;
use IEEE.std_logic_1164.all;
package wire is
function RES_FUNC(DATA : in std_logic_vector)
return std_logic;
subtype RESOLVED_STD is RES_FUNC std_logic;
end;
package body wire is
function RES_FUNC(DATA : in std_logic_vector)
return std_logic is
begin
for I in DATA'range loop
if DATA(I) = '1' then
return '1';
end if;
end loop;
return '0';
end;
end; |
3.6.Синтезируемость конструкций пакета
Листинг 3.7.Моделирование логической операции and
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity example_std is
port(x1 : in std_logic_vector(8 downto 0);
y1 : out std_logic_vector(8 downto 0));
end example_std;
architecture str of example_std is
constant w1 : std_logic_vector :=
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
begin
y1 <= x1 and w1;
end str;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test_example_std is
end;
architecture beh of test_example_std is
component example_std
port(x1 : in std_logic_vector(8 downto 0);
y1 : out std_logic_vector(8 downto 0));
end component;
signal x1, y1 : std_logic_vector (8 downto 0);
begin
p0 : example_std port map (x1, y1);
x1 <=
('U','U','U','U','U','U','U','U','U'),
('X','X','X','X','X','X','X','X','X') after 50 ns,
('0','0','0','0','0','0','0','0','0') after 100 ns,
('1','1','1','1','1','1','1','1','1') after 150 ns,
('Z','Z','Z','Z','Z','Z','Z','Z','Z') after 200 ns,
('W','W','W','W','W','W','W','W','W') after 250 ns,
('L','L','L','L','L','L','L','L','L') after 300 ns,
('H','H','H','H','H','H','H','H','H') after 350 ns,
('-','-','-','-','-','-','-','-','-') after 400 ns;
end beh; |
Листинг 3.8.VHDL-описание схемы (рис.3.7)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity example_std is
port (
x1 : in std_logic_vector (8 downto 0);
y1 : out std_logic_vector (8 downto 0)) ;
end example_std;
architecture str of example_std is
signal y1_0_EXMPLR : std_logic;
component GND port( Y: out std_logic );
end component;
begin
y1(8) <= y1_0_EXMPLR;
y1(7) <= y1_0_EXMPLR;
y1(6) <= y1_0_EXMPLR;
y1(5) <= x1(5);
y1(4) <= y1_0_EXMPLR;
y1(3) <= y1_0_EXMPLR;
y1(2) <= y1_0_EXMPLR;
y1(1) <= x1(1);
y1(0) <= y1_0_EXMPLR;
ix46 : GND port map (Y => y1_0_EXMPLR);
end str;
library ieee;
use ieee.std_logic_1164.all;
entity GND is
port( Y: out std_logic );
end;
architecture beh of GND is
begin
Y<= '0';
end beh; |
Листинг 3.9.Пример
package my is
type my_logic is ('1', '0', 'X', 'U');
end my;
library ieee;
use ieee.std_logic_1164.all;
use work.my.all;
entity dec is
port (
x1 : in std_logic;
x2 : in my_logic;
y1 : out std_logic_vector(2 downto 0);
y2 : out std_logic_vector(2 downto 0));
end dec;
architecture beh of dec is
begin
y1 <=
"000" when x1 = '0' else
"101" when x1 = '1' else
"010" when x1 = 'X' else
"111";
y2 <=
"000" when x2 = '0' else
"101" when x2 = '1' else
"010" when x2 = 'X' else
"111";
end beh; |
3.7.Использование неопределенных состояний don’t care
Листинг 3.11.VHDL-модель частичной функции
library ieee;
use ieee.std_logic_1164.all;
entity chast_one_f is
port (x1, x2, x3 : in std_logic;
F : out std_logic);
end;
architecture BEHAVIOR of chast_one_f is
begin
process (x1, x2, x3)
variable y : std_logic_vector(0 to 2);
variable f1 : std_logic;
begin
y := x1 & x2 & x3;
case y is
when "010" => f1 := '0';
when "100" => f1 := '0';
when "011" => f1 := '1';
when "101" => f1 := '1';
when others => f1 := '-';
end case;
F <= f1;
end process;
end BEHAVIOR; |
Листинг 3.12.VHDL-описание подсистемы sum_sc (вариант 1)
library ieee;
use ieee.std_logic_1164.all;
entity sum_sc is
port (a, b : in std_logic_vector(1 downto 0);
s : out std_logic_vector(2 downto 0));
end;
architecture BEHAVIOR of sum_sc is
begin
process (a, b)
variable y : std_logic_vector(3 downto 0);
variable s_pr : std_logic_vector(2 downto 0);
begin
y := a & b;
case y is
when "0000" => s_pr := "000";
when "0001" => s_pr := "001";
when "0010" => s_pr := "010";
when "0100" => s_pr := "001";
when "0101" => s_pr := "010";
when "0110" => s_pr := "011";
when "1000" => s_pr := "010";
when "1001" => s_pr := "011";
when "1010" => s_pr := "100";
when others => s_pr := "---";
end case;
s <= s_pr;
end process;
end BEHAVIOR; |
Листинг 3.13.VHDL-описание подсхемы sum_sc (вариант 2)
library ieee;
use ieee.std_logic_1164.all;
entity sum_sc is
port (a, b : in std_logic_vector (1 downto 0);
s : out std_logic_vector (2 downto 0));
end;
architecture BEHAVIOR of sum_sc is
begin
s <=
"000" when a & b = "0000" else
"001" when a & b = "0001" else
"010" when a & b = "0010" else
"001" when a & b = "0100" else
"010" when a & b = "0101" else
"011" when a & b = "0110" else
"010" when a & b = "1000" else
"011" when a & b = "1001" else
"100" when a & b = "1010" else
"---";
end BEHAVIOR; |
Листинг 3.14.VHDL-описание подсхемы umn_sc
library ieee;
use ieee.std_logic_1164.all;
entity umn_sc is
port (a, b : in std_logic_vector (2 downto 0);
u : out std_logic_vector (4 downto 0));
end;
architecture BEHAVIOR of umn_sc is
begin
process (a, b)
variable y : std_logic_vector (5 downto 0);
variable u_pr : std_logic_vector (4 downto 0);
begin
y := a & b;
case y is
when "000000" => u_pr := "00000";
when "000001" => u_pr := "00000";
when "000010" => u_pr := "00000";
when "000011" => u_pr := "00000";
when "000100" => u_pr := "00000";
when "001000" => u_pr := "00000";
when "001001" => u_pr := "00001";
when "001010" => u_pr := "00010";
when "001011" => u_pr := "00011";
when "001100" => u_pr := "00100";
when "010000" => u_pr := "00000";
when "010001" => u_pr := "00010";
when "010010" => u_pr := "00100";
when "010011" => u_pr := "00110";
when "010100" => u_pr := "01000";
when "011000" => u_pr := "00000";
when "011001" => u_pr := "00011";
when "011010" => u_pr := "00110";
when "011011" => u_pr := "01001";
when "011100" => u_pr := "10100";
when "100000" => u_pr := "00000";
when "100001" => u_pr := "00100";
when "100010" => u_pr := "01000";
when "100011" => u_pr := "10100";
when "100100" => u_pr := "10000";
when others => u_pr := "-----";
end case;
u <= u_pr;
end process;
end BEHAVIOR; |
Листинг 3.15.VHDL-описание схемы circ_chast (соединение трех подсхем)
library ieee;
use ieee.std_logic_1164.all;
entity circ_chast is
generic (
byte : natural := 2);
port (
a1,a2,a3,a4 : in std_logic_vector(byte-1 downto 0);
y : out std_logic_vector(2*byte downto 0));
end circ_chast;
architecture beh of circ_chast is
component sum_sc
port (a, b : in std_logic_vector (1 downto 0);
s : out std_logic_vector (2 downto 0));
end component;
component umn_sc
port (a, b : in std_logic_vector (2 downto 0);
u : out std_logic_vector(4 downto 0));
end component;
signal s1, s2 : std_logic_vector(byte downto 0);
begin
p1 : sum_sc port map (a => a1, b => a2, s => s1);
p2 : sum_sc port map (a => a3, b => a4, s => s2);
p3 : umn_sc port map (a => s1, b => s2, u => y);
end beh; |
Листинг 3.16.Алгоритмическое описание circ_f
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity circ_f is
generic (byte : natural := 2);
port (
a1,a2,a3,a4 : in std_logic_vector(byte-1 downto 0);
y : out std_logic_vector(2*byte downto 0));
end circ_f;
architecture beh of circ_f is
signal s1_int, s2_int : integer range 0 to 3;
signal s3_int, s4_int : integer range 0 to 3;
signal y_int : integer range 0 to 49;
begin
s1_int <= to_integer (unsigned (a1));
s2_int <= to_integer (unsigned (a2));
s3_int <= to_integer (unsigned (a3));
s4_int <= to_integer (unsigned (a4));
y_int <= (s1_int + s2_int) * (s3_int + s4_int);
y <= std_logic_vector(to_unsigned(y_int, 5));
end beh; |
Листинг 3.17.Алгоритмическое описание circ_full
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity circ_full is
generic (byte : natural := 2);
port (
a1,a2,a3,a4 : in std_logic_vector(byte-1 downto 0);
y : out std_logic_vector(2*byte+1 downto 0));
end circ_full;
architecture beh of circ_full is
begin
y <= std_logic_vector(
(unsigned('0' & a1)+unsigned(a2)) *
(unsigned('0' & a3)+unsigned(a4)) );
end beh; |
Листинг 3.18.Алгоритмическое описание circ_integ.Использование типа integer для входных, выходных портов
entity circ_integ is
port (
a1, a2, a3, a4 : in integer range 0 to 2;
y : out integer range 0 to 16);
end circ_integ;
architecture beh of circ_integ is
begin
y <= (a1 + a2) * (a3 + a4);
end beh; |
Листинг 3.19.VHDL-описание chast поведения схемы (рис.3.9) в виде одной системы частичных функций
library ieee;
use ieee.std_logic_1164.all;
entity chast is
port (
a1,a2,a3,a4 : in std_logic_vector(1 downto 0);
y : out std_logic_vector(4 downto 0));
end;
architecture BEHAVIOR of chast is
begin
process (a1, a2, a3, a4)
variable y1 : std_logic_vector (7 downto 0);
variable u_pr : std_logic_vector (4 downto 0);
begin
y1 := a1 & a2 & a3 & a4;
case y1 is
when "00000000" => u_pr := "00000";
when "00000001" => u_pr := "00000";
when "00000010" => u_pr := "00000";
when "00000011" => u_pr := "-----";
when "00000100" => u_pr := "00000";
when "00000101" => u_pr := "00000";
when "00000110" => u_pr := "00000";
-- (0 + 0) * (1 + 2) = 0
when "00000111" => u_pr := "-----";
-- (0 + 0) * (1 + 3)
-- результат не определен
when "00001000" => u_pr := "00000";
when "00001001" => u_pr := "00000";
when "00001010" => u_pr := "00000";
when "00001011" => u_pr := "-----";
when "00001100" => u_pr := "-----";
when "00001101" => u_pr := "-----";
when "00001110" => u_pr := "-----";
when "00001111" => u_pr := "-----";
when "00010000" => u_pr := "00000";
when "00010001" => u_pr := "00001";
-- (0 + 1) * (0 + 1) = 1
-- пропущены случаи от "00010010" до "10101000"
when "10101001" => u_pr := "01100";
when "10101010" => u_pr := "10000";
when others => u_pr := "-----";
end case;
y <= u_pr;
end process;
end BEHAVIOR; |
наверх
4.Пакет NUMERIC_STD
4.6.Синтезируемость конструкций пакета
Листинг 4.1.VHDL-описание двоичного счетчика count без использования пакета NUMERIC_STD
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity count is
generic (
byte : NATURAL := 4);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
d : out STD_LOGIC_VECTOR(byte-1
downto 0));
end count;
architecture beh_std of count is
signal d_i,d_t : STD_LOGIC_VECTOR(byte-1 downto 0);
begin
p1: process (clk, rst)
begin
if rst = '1' then
d_t <= (others => '0');
elsif
clk'event and clk='1' then
d_t <= d_i;
end if;
end process p1;
d_i <=
"0000" when d_t = "1111" else
"0001" when d_t = "0000" else
"0010" when d_t = "0001" else
"0011" when d_t = "0010" else
"0100" when d_t = "0011" else
"0101" when d_t = "0100" else
"0110" when d_t = "0101" else
"0111" when d_t = "0110" else
"1000" when d_t = "0111" else
"1001" when d_t = "1000" else
"1010" when d_t = "1001" else
"1011" when d_t = "1010" else
"1100" when d_t = "1011" else
"1101" when d_t = "1100" else
"1110" when d_t = "1101" else
"1111" when d_t = "1110" else
d_t;
d <= d_t;
end beh_std; |
Листинг 4.2.VHDL-описание двоичного счетчика count с использованием пакета NUMERIC_STD
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity count is
generic ( byte : NATURAL := 4);
port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
d : out STD_LOGIC_VECTOR(byte-1 downto 0));
end count;
architecture beh of count is
signal d_i : UNSIGNED(byte-1 downto 0);
begin
p1: process (clk, rst)
begin
if rst = '1' then
d_i <= (others => '0');
elsif
clk'event and clk='1' then
d_i <= d_i + 1;
end if;
end process p1;
d <= STD_LOGIC_VECTOR(d_i);
end beh; |
Листинг 4.3.Алгоритмическое описание умножителя mult
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity mult is
generic (byte : NATURAL := 4);
port ( a : in STD_LOGIC_VECTOR(byte-1 downto 0);
b : in STD_LOGIC_VECTOR(byte-1 downto 0);
y : out STD_LOGIC_VECTOR(2*byte-1 downto 0));
end mult;
architecture beh of mult is
begin
y <= STD_LOGIC_VECTOR(UNSIGNED(a) * UNSIGNED(b));
end beh; |
Листинг 4.4.Алгоритмическое описание сумматора add
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity add is
generic ( byte : NATURAL := 4);
port ( a : in STD_LOGIC_VECTOR(byte-1 downto 0);
b : in STD_LOGIC_VECTOR(byte-1 downto 0);
y : out NATURAL range 0 to (2**byte)-1);
end add;
architecture beh of add is
begin
y <= TO_INTEGER(UNSIGNED(a) + UNSIGNED(b));
end beh; |
Листинг 4.5.Алгоритмическое описание мультиплексора MUX
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity mux is
generic ( byte : NATURAL := 4);
port ( a : in STD_LOGIC_VECTOR(2*byte-1 downto 0);
b : in NATURAL range 0 to 2**byte-1;
ё : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(2*byte-1 downto 0));
end mux;
architecture beh of mux is
begin
y <= a when ё = '0' else
STD_LOGIC_VECTOR(TO_UNSIGNED(b,2*byte));
end beh; |
Листинг 4.6.Алгоритмическое описание VHDL-проекта convert
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity convert is
port ( a_i : in INTEGER;
b_u : in UNSIGNED(3 downto 0);
e_s : in SIGNED(1 downto 0);
c_s : out SIGNED(3 downto 0);
d_n : out NATURAL range 0 to 255;
f_s : out SIGNED(1 downto 0));
end convert;
architecture beh of convert is
begin
c_s <= TO_SIGNED(a_i,4);
d_n <= TO_INTEGER(b_u);
f_s <= TO_01(e_s);
end beh; |
Листинг 4.7.Структурное VHDL-описание логической схемы, реализующей VHDL-проект convert
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity convert is
port ( a_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
b_u : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;
e_s : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ;
c_s : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ;
d_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ;
f_s : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)) ;
end convert ;
architecture beh of convert is
signal d_n_7_EXMPLR: STD_LOGIC ;
component GND port( Y: out std_logic );
end component;
begin
c_s(3) <= a_i(3) ;
c_s(2) <= a_i(2) ;
c_s(1) <= a_i(1) ;
c_s(0) <= a_i(0) ;
d_n(7) <= d_n_7_EXMPLR ;
d_n(6) <= d_n_7_EXMPLR ;
d_n(5) <= d_n_7_EXMPLR ;
d_n(4) <= d_n_7_EXMPLR ;
d_n(3) <= b_u(3) ;
d_n(2) <= b_u(2) ;
d_n(1) <= b_u(1) ;
d_n(0) <= b_u(0) ;
f_s(1) <= e_s(1) ;
f_s(0) <= e_s(0) ;
ix22 : GND port map ( Y=>d_n_7_EXMPLR);
end beh ;
library ieee;
use ieee.std_logic_1164.all;
entity GND is
port( Y: out std_logic );
end;
architecture beh of GND is
begin
Y<= '0';
end beh; |
Листинг 4.8.Алгоритмическое описание VHDL-проекта to01_syn
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
entity to01_syn is
generic ( byte : NATURAL := 4);
port ( a_s : in SIGNED(byte-1 downto 0);
b_u : in UNSIGNED(byte-1 downto 0);
c_s : in SIGNED(byte-1 downto 0);
d_u : in UNSIGNED(byte-1 downto 0);
ya_s : out SIGNED(byte-1 downto 0);
yb_u : out UNSIGNED(byte-1 downto 0);
yc_s : out SIGNED(byte-1 downto 0);
yd_u : out UNSIGNED(byte-1 downto 0) );
end to01_syn;
architecture beh of to01_syn is
begin
ya_s <= TO_01(a_s);
yb_u <= TO_01(b_u);
yc_s <= TO_01(c_s, '0');
yd_u <= TO_01(d_u, 'X');
end beh; |
Листинг 4.9.Алгоритмическое описание VHDL-проекта resize_syn
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity resize_syn is
generic ( byte1 : NATURAL := 3;
byte2 : NATURAL := 5);
port ( a_s : in SIGNED(byte1-1 downto 0);
b_u : in UNSIGNED(byte1-1 downto 0);
ya_s : out SIGNED(byte2-1 downto 0);
yb_u : out UNSIGNED(byte2-1 downto 0));
end resize_syn;
architecture beh of resize_syn is
begin
ya_s <= RESIZE(a_s, byte2);
yb_u <= RESIZE(b_u, byte2);
end beh; |
Листинг 4.10.Алгоритмическое описание VHDL-проекта resize_syn_m
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity resize_syn_m is
generic ( byte1 : NATURAL := 5;
byte2 : NATURAL := 3);
port ( a_s : in SIGNED(byte1-1 downto 0);
b_u : in UNSIGNED(byte1-1 downto 0);
ya_s : out SIGNED(byte2-1 downto 0);
yb_u : out UNSIGNED(byte2-1 downto 0));
end resize_syn_m;
architecture beh of resize_syn_m is
begin
ya_s <= RESIZE(a_s, byte2);
yb_u <= RESIZE(b_u, byte2);
end beh; |
Листинг 4.11.Алгоритмическое описание проекта logic
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity logic is
port ( a : in UNSIGNED(2 downto 0);
y : out STD_LOGIC);
end logic;
architecture beh of logic is
begin
y<=(a(0) and a(1))or(a(1) and a(2))or(a(0) and a(2));
end beh; |
Листинг 4.12.Алгоритмическое описание схемы shift_fun сдвига вправо
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity shift_fun is
generic ( byte : NATURAL := 5);
port ( a_s : in SIGNED(byte-1 downto 0);
y_s : out SIGNED(byte-1 downto 0));
end shift_fun;
architecture beh of shift_fun is
begin
y_s <= SHIFT_RIGHT(a_s, 1);
end beh; |
Листинг 4.13.Алгоритмическое описание проекта comp
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity comp is
port ( a_s : in SIGNED(1 downto 0);
b_i : in INTEGER range -2 to 1;
a_u : in UNSIGNED(1 downto 0);
b_n : in NATURAL range 0 to 3;
c1 : out STD_LOGIC;
c2 : out STD_LOGIC);
end comp;
architecture beh of comp is
begin
c1 <= '1' when a_s < b_i else '0';
c2 <= '1' when a_u < b_n else '0';
end beh; |
Листинг 4.14.Алгоритмическое описание проекта add_syn
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity add_syn is
generic ( byte : NATURAL := 35);
port ( a_s : in SIGNED (byte-1 downto 0);
b_s : in SIGNED (byte-1 downto 0);
a_u : in UNSIGNED(byte-1 downto 0);
b_u : in UNSIGNED(byte-1 downto 0);
c_s : out SIGNED (byte downto 0);
c_u : out UNSIGNED(byte downto 0));
end add_syn;
architecture beh of add_syn is
begin
c_s <= a_s + (b_s(byte-1) & b_s);
c_u <= a_u + ('0' & b_u);
end beh; |
Листинг 4.15.Алгоритмическое описание проекта div_syn
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity div_syn is
generic ( byte : NATURAL := 6);
port ( a_s : in SIGNED(byte-1 downto 0);
c_s : out SIGNED(byte-1 downto 0));
end div_syn;
architecture beh of div_syn is
begin
c_s <= a_s / 4;
end beh; |
Листинг 4.16.Алгоритмическое описание проекта rem_syn
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity rem_syn is
generic ( byte : NATURAL := 6);
port ( a_s : in SIGNED(byte-1 downto 0);
c_s : out SIGNED(byte-1 downto 0));
end rem_syn;
architecture beh of rem_syn is
begin
c_s <= a_s rem 4;
end beh; |
Наверх
5.Пакет EXEMPLAR_1164
5.2.Использование атрибутов пакета при синтезе
Листинг 5.1. VHDL-код автомата Мура
library exemplar, ieee;
use exemplar.exemplar_1164.all;
use ieee.std_logic_1164.all;
entity Moore is
port(x : in std_logic_vector(4 downto 1);
clk : in std_logic;
y : out std_logic_vector(6 downto 1));
end Moore;
architecture beh of Moore is
type T_state is (a1, a2, a3, a4, a5, a6, a7, a8);
-- способ кодировани$ "собственный"
-- attribute TYPE_ENCODING of T_state : type is
-- ("0101", "0100", "0010","1000", "0001", "1100",
-- "0110", "0011");
-- способ кодировани$ "Gray"
-- attribute TYPE_ENCODING_STYLE of T_state : type is
-- Gray;
-- способ кодировани$ "Random"
-- attribute TYPE_ENCODING_STYLE of T_state : type is
-- Random;
-- способ кодировани$ "Binary"
attribute TYPE_ENCODING_STYLE of T_state : type is
Binary;
-- способ кодировани$ "Onehot"
-- attribute TYPE_ENCODING_STYLE of T_state : type is
-- Onehot;
-- способ кодировани$ "Twohot"
-- attribute TYPE_ENCODING_STYLE of T_state : type is
-- Twohot;
signal NEXT_state, state : T_state;
begin
NEXT_state <=
a2 when state = a1 else
a6 when state = a2 and x(1) = '0' else
a3 when state = a2 and x(2) = '1' else
a4 when state = a2 and x(3) = '1' else
a5 when state = a3 else
a1 when state = a4 and x(2) = '0' else
a7 when state = a4 else
a1 when state = a5 and x(2) = '0' else
a7 when state = a5 else
a5 when state = a6 and x(4) = '0' else
a8 when state = a6 and x(1) = '0' else
a8 when state = a7 else
a1 when state = a8 else state;
y <= "000000" when state = a1 else
"000101" when state = a2 else
"000110" when state = a3 else
"001000" when state = a4 else
"001001" when state = a5 else
"000010" when state = a6 else
"010000" when state = a7 else
"100000";
state <=
NEXT_state when clk'event and clk = '1' else
state;
end beh; |
Листинг 5.2.Пример задания атрибута noopt
entity resinthesis is
port(x1, x2, x3, clk : in bit;
y : out bit);
end resinthesis;
architecture beh of resinthesis is
component dlatch
port(d, clk : in bit;
q : out bit);
end component;
attribute noopt : boolean;
attribute noopt of dlatch : component is true;
-- attribute preserve_signal : boolean;
-- attribute preserve_signal of w2 : signal is TRUE;
signal w1, w2, w3, w4, w5, f : bit;
begin
w1 <= (not x1 and x2) or (x1 and not x2);
w2 <= (not x3 and w1) or (x3 and not w1);
w3 <= not w2;
w4 <= w3 and x1;
w5 <= w2 and x3;
f <= w4 or w5;
p0 : dlatch port map (d => f, clk => clk, q => y);
end beh; |
Листинг 5.3.Пример задания атрибута preserv_signal
process (x1, x2, x3)
variable w1, w2, w3, w4, w5 : bit;
attribute preserve_signal : boolean;
attribute preserve_signal of w1 : variable is true;
begin
w1 := (not x1 and x2) or (x1 and not x2);
w2 := (not x3 and w1) or (x3 and not w1);
w3 := not w2;
w4 := w3 and x1;
w5 := w2 and x3;
f <= w4 or w5;
end process; |
5.3.Функции и процедуры пакета
Листинг 5.7.Пример использования функции lb2bool
library ieee, exemplar;
use ieee.std_logic_1164.all;
use exemplar.exemplar_1164.all;
entity elbit2bool is
end elbit2bool;
architecture beh of elbit2bool is
signal x : std_ulogic;
signal s :std_ulogic_vector(8 downto 0):="UX01ZWLH-";
signal i : natural range 0 to 8 := 0;
signal y : boolean := true;
begin
i <= 0 after 10 ns when i = 8 else
i+1 after 10 ns;
x <= s(i);
y <= elb2bool(x);
end beh; |
Листинг 5.8.Пример использования функции lb2int
library ieee, exemplar;
use ieee.std_logic_1164.all;
use exemplar.exemplar_1164.all;
entity elbit2int is
end elbit2int;
architecture beh of elbit2int is
signal x: std_ulogic;
signal s: std_ulogic_vector(8 downto 0):="UX01ZWLH-";
signal i: natural range 0 to 8 := 8;
signal y: integer;
begin
i <= 8 after 10 ns when i=0 else
i-1 after 10 ns;
x <= s(i);
y <= elb2int(x);
end beh; |
Листинг 5.9.Пример использования процедур pullup,pulldn и trstmem
library ieee, exemplar;
use ieee.std_logic_1164.all;
use exemplar.exemplar_1164.all;
entity fpullup is
port (
x1, x2, x3 : in std_logic;
y1, y2, y3 : buffer std_logic);
end fpullup;
architecture beh of fpullup is
begin -- beh
y1 <= x1;
pullup(y1);
y2 <= x2;
pulldn(y2);
y3 <= x3;
trstmem(y3);
end beh; |
Листинг 5.10.Алгоритмическое описание схемы tree (файл ext01.vhd)
library ieee;
use ieee.std_logic_1164.all;
entity tree is
generic ( byte : natural := 3);
port (
a : in std_logic;
b : in std_logic_vector(byte-1 downto 0);
y : out std_logic_vector(byte-1 downto 0));
end tree;
architecture beh of tree is
signal sig : std_logic_vector(byte-1 downto 0);
begin
sig <= (others => (not a));
y <= sig and b;
end beh; |
Листинг 5.11.Скриптовый файл exp01.tcl
# Сброс установок
clean_all;
# Чтение VHDL-файла exp01.vhd
read -design tree exp01.vhd ;
# Чтение библиотеки синтеза
load_library bmk_little.syn;
# Синтез схемы
optimize -target bmk_little -macro -area
-effort standard -hierarchy flatten
optimize_timing
# Выдача отчета о сложности схемы
report_area -cell_usage
# Выдача отчета о задержке схемы
report_delay -num_paths 1 -critical_paths
# Сохранение нетлиста в формате VHDL
write exp01_syn.vhd; |
Листинг 5.13.Скриптовый файл (exp02.tcl)
clean_all;
read -design tree exp01.vhd ;
load_library bmk_little.syn;
# Установка атрибута для сигнала y(0)
set_attribute .work.tree.beh.y(0) -name
REQUIRED_TIME -value "2.50" -port
# Установка атрибута для сигнала y(1)
set_attribute .work.tree.beh.y(1) -name
REQUIRED_TIME -value "2.50" -port
# Установка атрибута для сигнала y(2)
set_attribute .work.tree.beh.y(2) -name
REQUIRED_TIME -value "2.50" -port
# Установка параметра требуемой задержки для
# всей схемы в целом
set input2output 2.9
optimize -target bmk_little -macro -area
-effort standard -hierarchy flatten
optimize_timing
report_area -cell_usage
report_delay -num_paths 1 -critical_paths
write exp02_syn.vhd; |
Листинг 5.15.Скриптовый файл exp03.tcl
clean_all;
read -design tree exp03.vhd ;
load_library bmk_little.syn;
# Установка параметра требуемой задержки 5 нс
# для всей схемы в целом
set input2output 5.00
optimize -target bmk_little -macro -area
-effort standard -hierarchy flatten
optimize_timing
report_area -cell_usage
report_delay -num_paths 1 -critical_paths
write exp03_syn.vhd; |
Листинг 5.18.Скриптовый файл exp04.tcl
clean_all;
read -design tree exp04.vhd ;
load_library bmk_little_dop.syn;
set -hierarchy flatten
set effort standard
set input2output 7.0
# Задание выходной нагрузки блока
set_attribute .work.tree.beh.y(0) -name
OUTPUT_LOAD -value "6.0" -port
set_attribute .work.tree.beh.y(1) -name
OUTPUT_LOAD -value "6.0" -port
set_attribute .work.tree.beh.y(3) -name
OUTPUT_LOAD -value "3.0" -port
# Задание максимально допустимой нагрузки по входу
# блока
set_attribute .work.tree.beh.a -name MAX_LOAD
-value "5.0" -port
# Задание выходного сопротивления внешнего выхода,
# управляющего входом
set_attribute .work.tree.beh.a -name
INPUT_DRIVE -value "0.5" -port
optimize -target bmk_little_dop -macro -area
-effort standard -hierarchy flatten
optimize_timing
report_area -cell_usage
report_delay -num_paths 1 -critical_paths
write exp04_syn.vhd; |
Наверх
6.Моделирование логический схем с использованием пакетов библиотеки VITAL
6.3.Синтез логической схемы
Листинг 6.1.Алгоритмическая VHDL-модель (файл tree.vhd)
library ieee;
use ieee.std_logic_1164.all;
entity tree is
generic ( byte : natural := 3);
port ( a : in std_logic;
b : in std_logic_vector(byte-1 downto 0);
y : out std_logic_vector(byte-1 downto 0));
end tree;
architecture beh of tree is
signal sig : std_logic_vector(byte-1 downto 0);
begin
sig <= (others => (not a));
y <= sig nand b;
end beh; |
Листинг 6.2.Tcl-скрипт (файл tree.tcl)
clean_all;
# Чтение VHDL-проекта
read -design tree tree.vhd ;
# Задание значений температуры, напряжения питания
# и разброса параметров технологического процесса,
# используемых для расчета задержек
set temp 80
set voltage 5.5
set process typical
# Чтение библиотеки синтеза
load_library bmk_little.syn;
# Задание ограничения на задержку схемы
set input2output 1.2
# Задание режимов оптимизации
optimize -target bmk_little -macro -area
-effort standard -hierarchy flatten
optimize_timing
# Выдача отчета о сложности схемы
report_area -cell_usage
# Выдача отчета о задержке (первый критический путь)
report_delay -num_paths 1 -critical_paths
# Установка объявлений на VHDL-пакеты
# (в структурное VHDL-описание схемы)
set vhdl_write_use_packages "library IEEE;
use IEEE.STD_LOGIC_1164.all;
library bmk_vital;
use bmk_vital.VCOMPONENTS.all;"
# Сохранение структурного VHDL-описания схемы
write tree_vital.vhd;
# Задание типа задержки в SDF-файле
set sdf_type maximum
# Сохранение SDF-файла
write tree_vital.sdf; |
Листинг 6.4.Структурное VHDL-описание синтезированной схемы tree (файл tree_vital.vhd)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library bmk_vital;
use bmk_vital.VCOMPONENTS.all;
entity tree is
port (
a : IN std_logic ;
b : IN std_logic_vector (2 DOWNTO 0) ;
y : OUT std_logic_vector (2 DOWNTO 0)) ;
end tree ;
architecture beh of tree is
signal nx64, nx76: std_logic ;
begin
ix3 : NA2 port map ( Y=>y(0), A=>nx76, B=>b(0));
ix7 : NA2 port map ( Y=>y(1), A=>nx76, B=>b(1));
nx64_EXMPLR : N port map ( Y=>nx64, A=>a);
y_2_EXMPLR_EXMPLR : NA2 port map ( Y=>y(2), A=>b(2), B=>nx64);
ix77 : N port map ( Y=>nx76, A=>a);
end beh ; |
Листинг 6.5.SDF-файл,соответствующий структурному VHDL-описанию (файл tree_vital.sdf)
(DELAYFILE
(SDFVERSION "2.0")
(DESIGN "tree")
(DATE "03/03/06 00:08:27")
(VENDOR "Exemplar Logic, Inc., Alameda")
(PROGRAM "LeonardoSpectrum Level 3")
(VERSION "2004a.30")
(DIVIDER /)
(VOLTAGE)
(PROCESS)
(TEMPERATURE)
(TIMESCALE 1 ns)
(CELL
(CELLTYPE "NA2")
(INSTANCE ix3)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.16) (::0.16))
(IOPATH B Y (::0.16) (::0.16)))))
(CELL
(CELLTYPE "NA2")
(INSTANCE ix7)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.16) (::0.16))
(IOPATH B Y (::0.16) (::0.16)))))
(CELL
(CELLTYPE "N")
(INSTANCE nx64_EXMPLR)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.46) (::0.47)))))
(CELL
(CELLTYPE "NA2")
(INSTANCE y_2_EXMPLR_EXMPLR)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.16) (::0.16))
(IOPATH B Y (::0.16) (::0.16)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix77)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.85) (::0.86)))))
) |
6.4.Моделирование логической схемы
Листинг 6.6.Тестирующая программа (файл tree_tb.vhd)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tree_tb is
generic ( byte : natural := 3);
end tree_tb;
architecture tb of tree_tb is
component tree
port (
a : in std_logic;
b : in std_logic_vector(byte-1 downto 0);
y : out std_logic_vector(byte-1 downto 0));
end component;
signal a : std_logic;
signal b : std_logic_vector(byte-1 downto 0);
signal y : std_logic_vector(byte-1 downto 0);
signal count : unsigned(byte downto 0) :=
(others => '0');
begin
count <= count + 1 after 2 ns;
a <= std_logic(count(0));
b <= std_logic_vector(count(byte downto 1));
d1: tree port map (a => a, b => b, y => y);
end tb; |
Наверх
7.Пакеты TEXTIO,STD_LOGIC_TEXTIO
7.3.Использование средств пакетов при моделировании
Листинг 7.1.Пример использования функций пакета TEXTIO
library std,ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity tst_textio is
generic (
rfile_name : string := "c:vhdexp00write.log";
wfile_name : string := "c:vhdexp00write.log");
end tst_textio;
architecture beh of tst_textio is
signal wint, rint : integer;
procedure pwrite is
file wfile : TEXT open write_mode is wfile_name;
variable l : line;
variable b : bit := '1';
variable bv : bit_vector(4 downto 0) := "10011";
variable int : integer := 32145;
variable r : real := 12.34523e12;
variable c : character := ' ';
variable t : time := 123 ms;
begin
write(l, b); -- запись в строку l значения
-- переменной b типа bit
write(l, c);
write(l, bv);
write(l, c);
write(l, int);
write(l, c);
write(l, r);
write(l, c);
write(l, t, right, 0, ms);
write(l, string'(" Example !!!"));
writeline(wfile, l); -- сохранение строки l
-- в файле write.log
end procedure;
procedure pread (
signal sb : out bit;
signal sbv : out bit_vector(4 downto 0);
signal sint : out integer;
signal sr : out real;
signal st : out time)
is
file rfile : TEXT open read_mode is rfile_name;
variable l : line;
variable b : bit;
variable bv : bit_vector(4 downto 0);
variable int : integer;
variable r : real;
variable c : character;
variable t : time;
begin
readline(rfile, l); -- чтение из файла write.log
-- строки символов
read(l, b); -- преобразование первого символа
-- строки l в значение переменной b
-- типа bit
read(l, bv);
read(l, int);
read(l, r);
read(l, t);
sb <= b;
sbv(4 downto 0) <= bv(4 downto 0);
sint <= int;
sr <= r;
st <= t;
end procedure;
signal b : bit;
signal bv : bit_vector(4 downto 0);
signal int : integer;
signal r : real;
signal c : character;
signal t : time;
begin
p1: process
begin
wait for 10 ns;
pwrite; -- вызов процедуры pwrite
pread(b,bv,int,r,t); -- вызов процедуры pread
end process p1;
end beh; |
Листинг 7.2.Пример использования функций пакета TEXTIO для BIT_VECTOR
library ieee;
use std.textio.all;
entity xxor is
end xxor;
architecture beh of xxor is
constant infilename : string := "c:vhdtest.in";
constant outfilename : string := "c:vhdtest.out";
signal a : bit_vector(1 downto 0);
signal b : bit_vector(1 downto 0);
signal y : bit_vector(1 downto 0);
file infile : TEXT open read_mode is infilename;
file outfile : TEXT open write_mode is outfilename;
procedure readtest (
file infile : TEXT ;
signal a : out bit_vector(1 downto 0);
signal b : out bit_vector(1 downto 0)) is
variable a_v, b_v : bit_vector(1 downto 0);
variable l : line;
begin
if not endfile(infile) then
-- чтение строки из файла
readline(infile, l);
-- если коментарий, то читаем еще строку
while l(1) = '#' loop
readline(infile,l);
end loop;
-- чтение вектора a из строки
read(l,a_v);
a <= a_v;
-- чтение вектора b из строки
read(l,b_v);
b <= b_v;
end if;
end readtest;
-- Процедура записи в файл результатов операции
procedure write_test (
file outfile : TEXT;
signal a : in bit_vector(1 downto 0);
signal b : in bit_vector(1 downto 0);
signal y : in bit_vector(1 downto 0)) is
variable l : line;
begin
write(l,a);
write(l,string'(" xor "));
write(l,b);
write(l,string'(" = "));
write(l,y);
writeline(outfile,l);
end procedure write_test;
begin
p1: process
begin
readtest(infile,a,b);
write_test(outfile,a,b,y);
wait for 10 ns;
end process p1;
y <= a xor b;
end beh; |
Листинг 7.3. Входной тестовый файл test.in для программы xxor
# a(1 downto 0) b(1 downto 0)
00 00
01 10
01 11
10 10
11 11 |
Листинг 7.5.Пример использований функций пакета STD_LOGIC_TEXTIO для типа STD_LOGIC_VECTOR
library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
entity xxor_std is
end xxor_std;
architecture beh of xxor_std is
constant infilename : string := "c:vhdtest.in";
constant outfilename : string := "c:vhdtest.out";
signal a : std_logic_vector(1 downto 0);
signal b : std_logic_vector(1 downto 0);
signal y : std_logic_vector(1 downto 0);
file infile : TEXT open read_mode is infilename;
file outfile : TEXT open write_mode is outfilename;
procedure readtest (
file infile : TEXT ;
signal a : out std_logic_vector(1 downto 0);
signal b : out std_logic_vector(1 downto 0)) is
variable a_v, b_v : std_logic_vector(1 downto 0);
variable l : line;
begin
if not endfile(infile) then
-- чтение строки из файла
readline(infile, l);
-- если коментарий, то читаем еще строку
while l(1) = '#' loop
readline(infile,l);
end loop;
-- чтение вектора a из строки
read(l,a_v);
a <= a_v;
-- чтение вектора b из строки
read(l,b_v);
b <= b_v;
end if;
end readtest;
-- Процедура записи в файл результатов операции
procedure write_test (
file outfile : TEXT;
signal a : in std_logic_vector(1 downto 0);
signal b : in std_logic_vector(1 downto 0);
signal y : in std_logic_vector(1 downto 0)) is
variable l : line;
begin
write(l,a);
write(l,string'(" xor "));
write(l,b);
write(l,string'(" = "));
write(l,y);
writeline(outfile,l);
end procedure write_test;
begin
p1: process
begin
readtest(infile,a,b);
write_test(outfile,a,b,y);
wait for 10 ns;
end process p1;
y <= a xor b;
end beh; |
Листинг 7.8.VHDL-модель ППЗУ
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity prom is
generic (
initfile : string := "");
port (
a : in std_logic_vector(2 downto 0);
wr : in std_logic;
di : in std_logic_vector(3 downto 0);
do : out std_logic_vector(3 downto 0));
end prom;
architecture beh of prom is
type mem_t is array(0 to 7)
of std_logic_vector(3 downto 0);
function init_mem_from_file
(constant filename : string) return mem_t is
file infile : text is filename;
variable l : line;
variable data : std_logic_vector(3 downto 0);
variable i : integer := 0;
variable mem :
mem_t := (others => (others => 'U'));
begin
while not endfile(infile) loop
readline(infile, l);
next when l(1) = '#';
read(l, data);
mem(i) := data;
i := i + 1;
end loop;
return mem;
end init_mem_from_file;
procedure save_rom_to_file (
constant filename : in string;
signal mem : in mem_t) is
file outfile : text open write_mode is filename;
variable l : line;
variable i : integer := 0;
begin
l := new string'("Произведена запись в ПЗУ. Карта памяти сохранена в файл rom.map");
writeline(output,l); -- вывод строки l в
-- консольную область
-- системы моделирования
l := new string'("# ROM was changed. New ROM map is:");
writeline(outfile,l); -- сохранение строки l
-- в файл
for i in 0 to 7 loop
write(l,mem(i));
writeline(outfile,l);
end loop;
end procedure save_rom_to_file;
signal mem : mem_t := init_mem_from_file(initfile);
begin
-- асинхронное чтение
do <= mem(to_integer(unsigned(a)));
-- синхронна$ запись
p1: process (wr)
begin
if wr'event and wr = '1' then
mem(to_integer(unsigned(a))) <= di;
save_rom_to_file(initfile,mem);
end if;
end process p1;
end beh; |
Листинг 7.9.Файл данных, записанных в ПЗУ (файл rom.map)
# Карта памяти ППЗУ 4х8 бит
0000
0001
0010
0100
#
1001
0110
0010
0100 |
Листинг 7.10.Тестирующая программа для VHDL-модели ППЗУ
library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
entity prom_tb is
end prom_tb;
architecture tb of prom_tb is
component prom
generic (
initfile : string);
port (
a : in std_logic_vector(2 downto 0);
wr : in std_logic;
di : in std_logic_vector(3 downto 0);
do : out std_logic_vector(3 downto 0));
end component;
constant infilename : string := "c:vhdtests.map";
constant initfile : string := "c:vhdrom.map";
signal a_i : std_logic_vector(2 downto 0);
signal wr_i : std_logic;
signal di_i : std_logic_vector(3 downto 0);
signal do_i : std_logic_vector(3 downto 0);
file inff : TEXT is infilename;
procedure readtest (
file infile : TEXT ;
a : out std_logic_vector(2 downto 0);
di : out std_logic_vector(3 downto 0);
wr : out std_logic) is
variable l : line;
begin
if not endfile(infile) then
-- чтение строки из файла
readline(infile, l);
-- выделение вектора адреса a из строки
read(l,a);
-- выделение вектора данных di из строки
read(l,di);
-- выделение сигнала записи wr из строки
read(l,wr);
end if;
end readtest;
begin
p1: process
variable a_v : std_logic_vector(2 downto 0);
variable di_v : std_logic_vector(3 downto 0);
variable wr_v : std_logic;
begin
readtest(inff,a_v,di_v,wr_v);
wr_i <= wr_v;
a_i <= a_v;
di_i <= di_v;
wait for 10 ns;
end process p1;
D1: prom
generic map (
initfile => initfile)
port map (
a => a_i,
wr => wr_i,
di => di_i,
do => do_i);
end tb; |
Листинг 7.11.Тестовые векторы для VHDL-модели ППЗУ (файл tests.map)
000 0000 0
001 0000 0
010 0000 0
011 0000 0
100 0000 0
101 0000 0
110 0000 0
111 1100 0
000 1100 1
001 0011 0
010 0011 1
011 0110 0
100 0110 1
101 1001 0
110 1001 1
111 0000 0
000 0000 0
001 0000 0
010 0000 0
011 0000 0
100 0000 0
101 0000 0
110 0000 0
111 1100 0 |
Наверх
8.Использование VHDL-пакетов в маршруте проектирования БМК
8.1.Пример проектирования арифметико-логического устройства
Листинг 8.1.Алгоритмическое описание блока alu (файл alu.vhd)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
generic (
byte_in : natural := 2;
byte_out : natural := 4);
port (
a : in std_logic_vector(byte_in-1 downto 0);
b : in std_logic_vector(byte_in-1 downto 0);
c : in std_logic_vector(1 downto 0);
y : out std_logic_vector(byte_out-1 downto 0));
end alu;
architecture beh of alu is
signal yy : unsigned(byte_out-1 downto 0);
begin
y <= std_logic_vector(yy);
yy <=
RESIZE(unsigned(a and b),byte_out) when c="00" else
RESIZE(unsigned(a or b),byte_out) when c="01" else
RESIZE(unsigned(a) * unsigned(b),byte_out)
when c="10" else
RESIZE((unsigned(a) + ('0'& unsigned(b)) ),byte_out)
when c="11" else
(others => 'X');
end beh; |
Листинг 8.2. Тестирующая программа для блока alu (файл alu_tb.vhd). Моделирование на всем пространстве входных наборов
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_tb is
end alu_tb;
architecture tb of alu_tb is
component alu
generic (
byte_in : natural;
byte_out : natural);
port (
a : in std_logic_vector(byte_in-1 downto 0);
b : in std_logic_vector(byte_in-1 downto 0);
c : in std_logic_vector(1 downto 0);
y : out std_logic_vector(byte_out-1 downto 0));
end component;
constant byte_in : natural := 2;
constant byte_out : natural := 4;
signal a_i : std_logic_vector(byte_in-1 downto 0);
signal b_i : std_logic_vector(byte_in-1 downto 0);
signal c_i : std_logic_vector(1 downto 0);
signal y_i : std_logic_vector(byte_out-1 downto 0);
signal counter :
unsigned((2*byte_in+2) downto 0) := (others => '0');
begin
counter <= counter + 1 after 5 ns;
a_i <= std_logic_vector(counter(1+byte_in downto 2));
b_i <= std_logic_vector(counter(1+byte_in+byte_in downto 2+byte_in));
c_i <= std_logic_vector(counter(1 downto 0));
x1: alu
generic map (
byte_in => byte_in,
byte_out => byte_out)
port map (a => a_i, b => b_i, c => c_i, y => y_i);
end tb; |
Листинг 8.3.Тестирующая программа для блока alu (файл tstb.vhd). Моделирование с проверкой ожидаемых реакций
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_TEXTIO.all;
use ieee.numeric_std.all;
entity tstb is
generic (
byte_in : natural := 2;
byte_out : natural := 4);
end;
architecture BEHAVIOR of tstb is
component alu
generic (
byte_in : natural := 2;
byte_out : natural := 4);
port (
a : in std_logic_vector(byte_in-1 downto 0);
b : in std_logic_vector(byte_in-1 downto 0);
c : in std_logic_vector(1 downto 0);
y : out std_logic_vector(byte_out-1 downto 0));
end component;
signal DATA:std_logic_vector ((3*byte_in)-1 downto 0);
signal a,b:std_logic_vector (byte_in-1 downto 0);
signal c : std_logic_vector(1 downto 0);
signal y : std_logic_vector(byte_out-1 downto 0);
signal OK : integer := 0;
begin
c <= (DATA(1), DATA (0)); b <= (DATA(3), DATA(2));
a <= (DATA(5), DATA(4));
p0: alu generic map (byte_in => 2, byte_out => 4)
port map (a, b, c, y);
process
file INFILE,OUTFILE, AWAIT_REACTION : text;
variable PTR,POKE, PREA :line;
variable DATA_IN: std_logic_vector
( (3*byte_in)-1 downto 0);
variable DATA_OUT: std_logic_vector
(byte_out-1 downto 0);
variable AWAIT_DATA_OUT:std_logic_vector
(byte_out-1 downto 0);
begin
file_open(INFILE,"IN.TST",read_mode);
file_open(AWAIT_REACTION,"AWAIT_OUT.TST",read_mode);
file_open(OUTFILE,"OUT.TST",write_mode);
while not (endfile(INFILE)) loop
wait for 20 ns;
readline(INFILE,PTR);
read(PTR,DATA_IN);
DATA <= DATA_IN;
readline(AWAIT_REACTION,PREA);
read(PREA,AWAIT_DATA_OUT);
wait for 20 ns;
DATA_OUT := y;
write(POKE,DATA_OUT);
writeline(OUTFILE,POKE);
if (AWAIT_DATA_OUT = DATA_OUT) then null;
else OK <= OK + 1;
end if;
end loop;
file_close(OUTFILE);
file_close(INFILE);
file_close(AWAIT_REACTION);
if (OK = 0) then
assert(FALSE) report "Done!" severity WARNING;
else
assert(FALSE) report "ERROR!" severity FAILURE;
end if;
wait;
end process;
end; |
Листинг 8.4.Скрипт для синтеза блока alu (файл alu.tcl)
clean_all;
read -design alu alu.vhd ;
load_library bmk.syn;
set -hierarchy flatten
set effort standard
set input2output 5.0
optimize -target bmk -macro -area -effort standard
-hierarchy flatten
optimize_timing
report_area
report_delay -num_paths 1 -critical_paths
# Сохранение VHDL-описания логической схемы
write alu_syn.vhd;
# Задание типа задержки
# set sdf_type maximum
# Сохранение SDF-файла
write alu_syn.sdf; |
Листинг 8.11. VHDL-модель декрементора
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decr_6 is
port(di6, di5, di4, di3, di2, di1 : in STD_LOGIC;
du7, du6, du5, du4, du3, du2, du1 : out std_logic);
end;
architecture beh of decr_6 is
signal e: integer range 0 to 64;
signal DIN : integer range 0 to 63;
signal a : std_logic_vector ( 6 downto 1);
signal D : std_logic_vector ( 7 downto 1);
begin
a <= (di6, di5, di4,di3, di2, di1);
DIN <= to_integer(unsigned(a));
e <= DIN + 1;
D <= std_logic_vector(to_unsigned(e,7));
du7 <= D(7);
du6 <= D(6);
du5 <= D(5);
du4 <= D(4);
du3 <= D(3);
du2 <= D(2);
du1 <= D(1);
end beh; |
Наверх
Приложение 1.Описание библиотеки bmk_little для программы lGen (файл bmk_little.lgn)
LIBRARY bmk_little (
GATE GND (
INPUTS;
OUTPUTS Y;
FUNCTION ( Y = CONST0; );
AREA = 1.000; );
GATE VCC (
INPUTS;
OUTPUTS Y;
FUNCTION ( Y = CONST1; );
AREA = 1.000; );
GATE N (
INPUTS A;
OUTPUTS Y;
FUNCTION ( Y = !A; );
AREA = 2.000;
INPUT A (
LIN = 1.000;
DELAY (
PROP = (0.09,0.1);
DRIVE = (0.5,0.5);););
OUTPUT Y ( LMAX = 4.000; ); );
GATE NA2 (
INPUTS A,B;
OUTPUTS Y;
FUNCTION ( Y = !(A*B); );
AREA = 3.000;
INPUT A (
LIN = 1.000;
DELAY (
PROP = (0.2,0.2);
DRIVE = (1.0,1.0);););
INPUT B (
LIN = 1.000;
DELAY (
PROP = (0.2,0.2);
DRIVE = (1.0,1.0);););
OUTPUT Y ( LMAX = 4.000; ); );
GATE FDRS (
INPUTS C,D,R,S;
OUTPUTS Q;
FUNCTION (DFF(S,R,D,C,Q,-););
AREA = 32.000;
INPUT D (
LIN = 1.000;
DELAY C (
SETUP = (2.0,2.0);););
INPUT C (
LIN = 1.000;
DELAY Q (
PROP = (1.0,1.0);
DRIVE = (0.5,0.5);););
INPUT R (
LIN = 1.000;
DELAY Q (
PROP = (1.0,1.0);
DRIVE = (0.5,0.5);););
INPUT S (
LIN = 1.000;
DELAY Q (
PROP = (1.0,1.0);
DRIVE = (0.5,0.5);););
OUTPUT Q ( LMAX = 16.000; ); );
###
### Global variable
###
set area_units = step;
set delay_units = ns;
set lib_version = 03.01.2006;
set max_temp = 85;
set max_voltage = 6.0;
set min_temp = -40;
set min_voltage = 2.7;
set temp_slope = 0.0025;
set voltage_slope = -0.140000;
set nominal_process = typical;
set nominal_temp = 27;
set nominal_voltage = 3.300000;
set fast_process = 0.900000;
set typical_process = 1;
set worst_process = 1.100000;
set opt_for_area_weights = 1 0.010000 0.100000 0;
set opt_for_speed_weights = 0.010000 1 0.100000 0;
set rep_logic = true;
) |
Наверх
Приложение 2. VHDL-описания элементов библиотеки bmk_little
1.Файл bmk.vhd, содержащий описания элементов с ненулевыми задержками
library ieee;
use ieee.std_logic_1164.all;
entity GND is
port( Y : out std_logic );
end;
architecture beh of GND is
begin
Y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity VCC is
port( Y : out std_logic );
end;
architecture beh of VCC is
begin
Y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity N is
generic (
del : time := 160 ps);
port (
A : in std_logic;
Y : out std_logic);
end N;
architecture beh of N is
begin
Y <= not A after del;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity NA2 is
generic (
del : time := 275 ps);
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic);
end NA2;
architecture beh of NA2 is
begin
Y <= not (A and B) after del;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity FDRS is
generic (
del : time := 1300 ps);
port (
D : in std_logic;
C : in std_logic;
R : in std_logic;
S : in std_logic;
Q : out std_logic);
end FDRS;
architecture beh of FDRS is
begin
p1 : process (C, R, S)
begin
if R = '1' then
Q <= '0' after del;
elsif S = '1' then
Q <= '1' after del;
elsif C'event and C = '1' then
Q <= D after del;
end if;
end process p1;
end beh; |
2.Файл bmk_pack.vhd, содержащий декларации элементов библиотеки bmk_little
library ieee;
use ieee.std_logic_1164.all;
package bmk_pack is
component GND
port (
Y : out std_logic);
end component;
component VCC
port (
Y : out std_logic);
end component;
component N
generic (
del : time);
port (
A : in std_logic;
Y : out std_logic);
end component;
component NA2
generic (
del : time);
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic);
end component;
component FDRS
generic (
del : time);
port (
D : in std_logic;
C : in std_logic;
R : in std_logic;
S : in std_logic;
Q : out std_logic);
end component; end bmk_pack; |
Наверх
Приложение 3. VITAL-библиотека bmk_little 1.Файл bmk_VITAL.vhd
----- CELL FDRS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity FDRS is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_R_q : VitalDelayType01 := (1806.000 ps, 1042.000 ps);
tpd_S_q : VitalDelayType01 := (1806.000 ps, 1042.000 ps);
tpd_C_q : VitalDelayType01 := (1299.000 ps, 1270.000 ps);
tsetup_D_C : VitalDelayType := 600.000 ps;
thold_D_C : VitalDelayType := 500.000 ps;
tipd_D : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_C : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_R : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_S : VitalDelayType01 := (0.000 ps, 0.000 ps));
port(
D : in STD_ULOGIC;
C : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC;
q : out STD_ULOGIC);
attribute VITAL_LEVEL0 of FDRS : entity is TRUE;
end FDRS;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library bmk;
use bmk.VTABLES.all;
architecture VITAL of FDRS is
attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
SIGNAL D_ipd : STD_ULOGIC := 'X';
SIGNAL C_ipd : STD_ULOGIC := 'X';
SIGNAL R_ipd : STD_ULOGIC := 'X';
SIGNAL S_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (C_ipd, C, tipd_C);
VitalWireDelay (R_ipd, R, tipd_R);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, C_ipd, R_ipd, S_ipd)
-- timing check results
VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0';
VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 4);
VARIABLE D_delayed : STD_ULOGIC := 'X';
VARIABLE C_delayed : STD_ULOGIC := 'X';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS q_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE q_GlitchData : VitalGlitchDataType;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_C_posedge,
TimingData => Tmkr_D_C_posedge,
TestSignal => D_ipd,
TestSignalName => "D",
TestDelay => 0 ps,
RefSignal => C_ipd,
RefSignalName => "C",
RefDelay => 0 ps,
SetupHigh => tsetup_D_C,
SetupLow => tsetup_D_C,
HoldHigh => thold_D_C,
HoldLow => thold_D_C,
CheckEnabled =>
TO_X01(( S_ipd ) OR ( R_ipd ) ) /= '1',
RefTransition => 'R',
HeaderMsg => InstancePath & "/FDRS",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_C_posedge;
VitalStateTable(
Result => q_zd,
PreviousDataIn => PrevData_q,
StateTable => FDRS_q_tab,
DataIn => (
C_delayed, D_delayed, S_ipd, C_ipd, R_ipd));
q_zd := Violation XOR q_zd;
D_delayed := D_ipd;
C_delayed := C_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
GlitchData => q_GlitchData,
OutSignalName => "q",
OutTemp => q_zd,
Paths => (0 => (R_ipd'last_event, tpd_R_q, TRUE),
1 => (S_ipd'last_event, tpd_S_q, TRUE),
2 => (C_ipd'last_event, tpd_C_q, TRUE)),
Mode => OnDetect,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end VITAL;
configuration CFG_FDRS_VITAL of FDRS is
for VITAL
end for;
end CFG_FDRS_VITAL;
----- CELL GND -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity GND is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True);
port(
Y : out STD_ULOGIC := '0');
attribute VITAL_LEVEL0 of GND : entity is TRUE;
end GND;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library bmk;
use bmk.VTABLES.all;
architecture VITAL of GND is
attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
-- empty
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
Y <= '0';
end VITAL;
configuration CFG_GND_VITAL of GND is
for VITAL
end for;
end CFG_GND_VITAL;
----- CELL N -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity N is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (160.000 ps, 135.000 ps);
tipd_A : VitalDelayType01 := (0.000 ps, 0.000 ps));
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
attribute VITAL_LEVEL0 of N : entity is TRUE;
end N;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library bmk;
use bmk.VTABLES.all;
architecture VITAL of N is
attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
SIGNAL A_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := (NOT A_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
GlitchData => Y_GlitchData,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)),
Mode => OnDetect,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end VITAL;
configuration CFG_N_VITAL of N is
for VITAL
end for;
end CFG_N_VITAL;
----- CELL NA2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity NA2 is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (179.000 ps, 272.000 ps);
tpd_B_Y : VitalDelayType01 := (150.000 ps, 275.000 ps);
tipd_A : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_B : VitalDelayType01 := (0.000 ps, 0.000 ps));
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
attribute VITAL_LEVEL0 of NA2 : entity is TRUE;
end NA2;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library bmk;
use bmk.VTABLES.all;
architecture VITAL of NA2 is
attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
SIGNAL A_ipd : STD_ULOGIC := 'X';
SIGNAL B_ipd : STD_ULOGIC := 'X';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_LOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := (NOT ((B_ipd) AND (A_ipd)));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
GlitchData => Y_GlitchData,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE),
1 => (B_ipd'last_event, tpd_B_Y, TRUE)),
Mode => OnDetect,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);
end process;
end VITAL;
configuration CFG_NA2_VITAL of NA2 is
for VITAL
end for;
end CFG_NA2_VITAL;
----- CELL VCC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity VCC is
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True);
port(
Y : out STD_ULOGIC := '1');
attribute VITAL_LEVEL0 of VCC : entity is TRUE;
end VCC;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library bmk;
use bmk.VTABLES.all;
architecture VITAL of VCC is
attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
-- empty
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
Y <= '1';
end VITAL;
configuration CFG_VCC_VITAL of VCC is
for VITAL
end for;
end CFG_VCC_VITAL;
---- end of library ---- |
2.Файл bmk_Vcomponents.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on
package VCOMPONENTS is
constant DefaultTimingChecksOn : Boolean := True;
constant DefaultXon : Boolean := False;
constant DefaultMsgOn : Boolean := True;
----- Component FDRS -----
component FDRS
-- synopsys translate_off
generic(
TimingChecksOn: Boolean := DefaultTimingChecksOn;
InstancePath: STRING := "*";
Xon: Boolean := DefaultXon;
MsgOn: Boolean := DefaultMsgOn;
tpd_R_q : VitalDelayType01 := (1806.000 ps, 1042.000 ps);
tpd_S_q : VitalDelayType01 := (1806.000 ps, 1042.000 ps);
tpd_C_q : VitalDelayType01 := (1299.000 ps, 1270.000 ps);
tsetup_D_C : VitalDelayType := 600.000 ps;
thold_D_C : VitalDelayType := 500.000 ps;
tipd_D : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_C : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_R : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_S : VitalDelayType01 := (0.000 ps, 0.000 ps));
-- synopsys translate_on
port(
D : in STD_ULOGIC;
C : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC;
q : out STD_ULOGIC);
end component;
----- Component GND -----
component GND
-- synopsys translate_off
generic(
TimingChecksOn: Boolean := DefaultTimingChecksOn;
InstancePath: STRING := "*";
Xon: Boolean := DefaultXon;
MsgOn: Boolean := DefaultMsgOn);
-- synopsys translate_on
port(
Y : out STD_ULOGIC := '0');
end component;
----- Component N -----
component N
-- synopsys translate_off
generic(
TimingChecksOn: Boolean := DefaultTimingChecksOn;
InstancePath: STRING := "*";
Xon: Boolean := DefaultXon;
MsgOn: Boolean := DefaultMsgOn;
tpd_A_Y : VitalDelayType01 := (160.000 ps, 135.000 ps);
tipd_A : VitalDelayType01 := (0.000 ps, 0.000 ps));
-- synopsys translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
----- Component NA2 -----
component NA2
-- synopsys translate_off
generic(
TimingChecksOn: Boolean := DefaultTimingChecksOn;
InstancePath: STRING := "*";
Xon: Boolean := DefaultXon;
MsgOn: Boolean := DefaultMsgOn;
tpd_A_Y : VitalDelayType01 := (179.000 ps, 272.000 ps);
tpd_B_Y : VitalDelayType01 := (150.000 ps, 275.000 ps);
tipd_A : VitalDelayType01 := (0.000 ps, 0.000 ps);
tipd_B : VitalDelayType01 := (0.000 ps, 0.000 ps));
-- synopsys translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
----- Component VCC -----
component VCC
-- synopsys translate_off
generic(
TimingChecksOn: Boolean := DefaultTimingChecksOn;
InstancePath: STRING := "*";
Xon: Boolean := DefaultXon;
MsgOn: Boolean := DefaultMsgOn);
-- synopsys translate_on
port(
Y : out STD_ULOGIC := '1');
end component;
end VCOMPONENTS;
---- end of VITAL components library ---- |
3.Файл bmk_Vtables.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
-- synopsys translate_on
package VTABLES is
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B';
-- valid clock signal (non-rising)
CONSTANT FDRS_q_tab : VitalStateTableType := (
( L, L, L, H, x, x, L ),
( L, H, x, H, L, x, H ),
( H, x, L, x, L, x, S ),
( x, x, L, L, L, x, S ),
( x, x, H, x, L, x, H ),
( x, x, x, x, H, x, L ));
end VTABLES;
---- end of VITAL tables library ---- |
Наверх
Приложение 4. Моделирование схемы АЛУ
1.Структурное описание (netlist) синтезированной схемы alu (файл alu_syn.vhd)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.bmk_pack.all;
entity alu is
generic (
byte_in : natural := 2;
byte_out : natural := 4);
port (
a : IN std_logic_vector (1 DOWNTO 0) ;
b : IN std_logic_vector (1 DOWNTO 0) ;
c : IN std_logic_vector (1 DOWNTO 0) ;
y : OUT std_logic_vector (3 DOWNTO 0)) ;
end alu ;
architecture beh of alu is
signal nx6, nx110, nx130, nx132, nx112, nx142, nx143, nx144, nx145, nx146,
nx147, NOT_nx118, nx107, nx148, nx149, nx150, nx151, nx152, nx153,
nx154, nx155, nx156, nx127: std_logic ;
begin
ix89 : NO3 port map ( Y=>y(3), A=>nx6, B=>c(0), C=>nx107);
ix7 : NA3 port map ( Y=>nx6, A=>b(0), B=>a(0), C=>c(1));
ix37 : NAO2 port map ( Y=>y(0), A=>nx110, B=>c(0), C=>nx112);
ix111 : NA3O2 port map ( Y=>nx110, A=>c(0), B=>nx6, C=>a(0), D=>b(0));
ix25 : NAO3 port map ( Y=>y(2), A=>nx130, B=>nx6, C=>nx132, D=>nx127);
ix131 : NA4 port map ( Y=>nx130, A=>nx112, B=>c(1), C=>a(1), D=>b(1));
ix133 : N port map ( Y=>nx132, A=>c(0));
ix113 : NA2 port map ( Y=>nx112, A=>b(0), B=>a(0));
ix157 : N port map ( Y=>nx142, A=>c(1));
ix158 : NO2 port map ( Y=>nx143, A=>nx142, B=>c(0));
ix159 : N port map ( Y=>nx144, A=>a(1));
ix160 : N port map ( Y=>nx145, A=>b(0));
ix161 : N port map ( Y=>nx146, A=>b(1));
ix162 : N port map ( Y=>nx147, A=>a(0));
NOT_ix118: NAO22 port map ( Y=>NOT_nx118, A=>nx144, B=>nx145, C=>
nx146, D=>nx147);
ix107 : NA2 port map ( Y=>nx107, A=>b(1), B=>a(1));
ix163 : NA3O2 port map ( Y=>nx148, A=>nx143, B=>NOT_nx118, C=>nx112, D=>
nx107);
ix164 : NA3O2 port map ( Y=>nx149, A=>c(0), B=>nx142, C=>b(1), D=>a(1));
ix165 : NOA22 port map ( Y=>nx150, A=>b(1), B=>a(1), C=>nx146, D=>nx144);
ix166 : NOA2 port map ( Y=>nx151, A=>c(1), B=>nx146, C=>nx144);
ix167 : N port map ( Y=>nx152, A=>nx112);
ix168 : NOA3 port map ( Y=>nx153, A=>nx151, B=>nx152, C=>c(1), D=>c(0));
ix169 : NA3O2 port map ( Y=>nx154, A=>nx148, B=>nx149, C=>nx150, D=>nx153
);
ix170 : A2 port map ( Y=>nx155, A=>c(1), B=>c(0));
ix171 : NOA3 port map ( Y=>nx156, A=>nx154, B=>nx112, C=>nx150, D=>nx155
);
yy_1: N port map ( Y=>y(1), A=>nx156);
ix127: NO2 port map ( Y=>nx127, A=>b(1), B=>a(1));
end beh ; |
2.SDF-файл синтезированной схемы (alu_syn.sdf)
(DELAYFILE
(SDFVERSION "2.0")
(DESIGN "alu")
(DATE "01/13/06 12:12:17")
(VENDOR "Exemplar Logic, Inc., Alameda")
(PROGRAM "LeonardoSpectrum Level 3")
(VERSION "2004a.30")
(DIVIDER /)
(VOLTAGE)
(PROCESS)
(TEMPERATURE)
(TIMESCALE 1 ns)
(CELL
(CELLTYPE "NO3")
(INSTANCE ix89)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(IOPATH A Y (::0.54) (::0.17))
(IOPATH B Y (::0.56) (::0.18))
(IOPATH C Y (::0.53) (::0.18)))))
(CELL
(CELLTYPE "NA3")
(INSTANCE ix7)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(IOPATH A Y (::0.52) (::0.83))
(IOPATH B Y (::0.47) (::0.84))
(IOPATH C Y (::0.53) (::0.84)))))
(CELL
(CELLTYPE "NAO2")
(INSTANCE ix37)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(IOPATH A Y (::0.15) (::0.28))
(IOPATH B Y (::0.30) (::0.25))
(IOPATH C Y (::0.36) (::0.27)))))
(CELL
(CELLTYPE "NA3O2")
(INSTANCE ix111)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.29) (::0.52))
(IOPATH B Y (::0.28) (::0.51))
(IOPATH C Y (::0.22) (::0.52))
(IOPATH D Y (::0.64) (::0.51)))))
(CELL
(CELLTYPE "NAO3")
(INSTANCE ix25)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::1.00) (::0.67))
(IOPATH B Y (::1.00) (::0.67))
(IOPATH C Y (::1.00) (::0.67))
(IOPATH D Y (::1.00) (::0.67)))))
(CELL
(CELLTYPE "NA4")
(INSTANCE ix131)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.45) (::0.92))
(IOPATH B Y (::0.44) (::0.89))
(IOPATH C Y (::0.40) (::0.81))
(IOPATH D Y (::0.34) (::0.71)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix133)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.21) (::0.18)))))
(CELL
(CELLTYPE "NA2")
(INSTANCE ix113)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.72) (::0.77))
(IOPATH B Y (::0.69) (::0.77)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix157)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.28) (::0.23)))))
(CELL
(CELLTYPE "NO2")
(INSTANCE ix158)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.54) (::0.24))
(IOPATH B Y (::0.52) (::0.22)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix159)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.33) (::0.28)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix160)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.21) (::0.18)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix161)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.33) (::0.28)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix162)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.21) (::0.18)))))
(CELL
(CELLTYPE "NAO22")
(INSTANCE NOT_ix118)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.73) (::0.50))
(IOPATH B Y (::0.74) (::0.29))
(IOPATH C Y (::0.52) (::0.38))
(IOPATH D Y (::0.72) (::0.31)))))
(CELL
(CELLTYPE "NA2")
(INSTANCE ix107)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.39) (::0.47))
(IOPATH B Y (::0.36) (::0.47)))))
(CELL
(CELLTYPE "NA3O2")
(INSTANCE ix163)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.30) (::0.52))
(IOPATH B Y (::0.29) (::0.52))
(IOPATH C Y (::0.22) (::0.52))
(IOPATH D Y (::0.65) (::0.52)))))
(CELL
(CELLTYPE "NA3O2")
(INSTANCE ix164)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.31) (::0.53))
(IOPATH B Y (::0.29) (::0.53))
(IOPATH C Y (::0.22) (::0.53))
(IOPATH D Y (::0.67) (::0.53)))))
(CELL
(CELLTYPE "NOA22")
(INSTANCE ix165)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.93) (::0.50))
(IOPATH B Y (::0.71) (::0.57))
(IOPATH C Y (::0.48) (::0.55))
(IOPATH D Y (::0.53) (::0.44)))))
(CELL
(CELLTYPE "NOA2")
(INSTANCE ix166)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(IOPATH A Y (::0.42) (::0.22))
(IOPATH B Y (::0.43) (::0.35))
(IOPATH C Y (::0.54) (::0.15)))))
(CELL
(CELLTYPE "N")
(INSTANCE ix167)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.21) (::0.18)))))
(CELL
(CELLTYPE "NOA3")
(INSTANCE ix168)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.30) (::0.21))
(IOPATH B Y (::0.66) (::0.75))
(IOPATH C Y (::0.53) (::0.69))
(IOPATH D Y (::0.75) (::0.76)))))
(CELL
(CELLTYPE "NA3O2")
(INSTANCE ix169)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.29) (::0.51))
(IOPATH B Y (::0.28) (::0.51))
(IOPATH C Y (::0.21) (::0.51))
(IOPATH D Y (::0.64) (::0.51)))))
(CELL
(CELLTYPE "A2")
(INSTANCE ix170)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.56) (::0.53))
(IOPATH B Y (::0.56) (::0.48)))))
(CELL
(CELLTYPE "NOA3")
(INSTANCE ix171)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(PORT C (::0.00) (::0.00))
(PORT D (::0.00) (::0.00))
(IOPATH A Y (::0.30) (::0.21))
(IOPATH B Y (::0.66) (::0.74))
(IOPATH C Y (::0.53) (::0.68))
(IOPATH D Y (::0.74) (::0.76)))))
(CELL
(CELLTYPE "N")
(INSTANCE yy_1)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(IOPATH A Y (::0.16) (::0.14)))))
(CELL
(CELLTYPE "NO2")
(INSTANCE ix127)
(DELAY
(ABSOLUTE
(PORT A (::0.00) (::0.00))
(PORT B (::0.00) (::0.00))
(IOPATH A Y (::0.52) (::0.24))
(IOPATH B Y (::0.50) (::0.22)))))
) |
3.RTL-описание схемы alu после команды unmap (файл alu_RTL.vhd)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity alu is
port (
a : IN std_logic_vector (1 DOWNTO 0) ;
b : IN std_logic_vector (1 DOWNTO 0) ;
c : IN std_logic_vector (1 DOWNTO 0) ;
y : OUT std_logic_vector (3 DOWNTO 0)) ;
end alu ;
architecture beh of alu is
signal nx6, nx110, nx130, nx132, nx112, nx142, nx143, nx144, nx145, nx146,
nx147, NOT_nx118, nx107, nx148, nx149, nx150, nx151, nx152, nx153,
nx154, nx155, nx156, nx127, nx3, nx4_dup_0, nx4, nx5, nx172,
nx4_dup_0_dup_173, nx174, nx175, nx176, nx4_dup_0_dup_177, nx178,
nx179, nx4_dup_0_dup_181, nx182, nx183, nx184, nx8, nx7,
nx4_dup_0_dup_186, nx187, nx188, nx189, nx190, nx191,
nx4_dup_0_dup_193, nx194, nx195, nx196, nx197, nx198, nx2, nx200,
nx202, nx203, nx4_dup_0_dup_206, nx207, nx208, nx209, nx210, nx10,
nx212, nx213, nx4_dup_0_dup_216, nx217, nx218, nx219, nx220, nx221,
nx4_dup_0_dup_224, nx225, nx226, nx227, nx228, nx229,
nx4_dup_0_dup_232, nx233, nx234, nx235, nx236, nx237, nx238, nx14,
nx16, nx18, nx241, nx4_dup_0_dup_242, nx243, nx244, nx245,
nx4_dup_0_dup_249, nx250, nx251, nx252, nx253, nx254, nx255, nx256,
nx4_dup_0_dup_259, nx260, nx261, nx262, nx263, nx264,
nx4_dup_0_dup_269, nx270, nx271, nx272, nx273, nx274, nx275, nx276,
nx278, nx279: std_logic ;
begin
nx3 <= NOT nx6 ;
nx4_dup_0 <= NOT c(0) ;
nx4 <= nx3 AND nx4_dup_0 ;
nx5 <= NOT nx107 ;
y(3) <= nx4 AND nx5 ;
nx172 <= NOT c(1) ;
nx4_dup_0_dup_173 <= NOT a(0) ;
nx174 <= nx172 OR nx4_dup_0_dup_173 ;
nx175 <= NOT b(0) ;
nx6 <= nx174 OR nx175 ;
nx176 <= NOT c(0) ;
nx4_dup_0_dup_177 <= NOT nx112 ;
nx178 <= nx176 AND nx4_dup_0_dup_177 ;
nx179 <= NOT nx110 ;
y(0) <= nx178 OR nx179 ;
nx4_dup_0_dup_181 <= NOT a(0) ;
nx182 <= NOT b(0) ;
nx183 <= nx4_dup_0_dup_181 AND nx182 ;
nx184 <= NOT nx6 ;
nx8 <= nx183 OR nx184 ;
nx7 <= NOT c(0) ;
nx110 <= nx8 OR nx7 ;
nx4_dup_0_dup_186 <= NOT nx6 ;
nx187 <= NOT nx132 ;
nx188 <= nx4_dup_0_dup_186 AND nx187 ;
nx189 <= NOT nx127 ;
nx190 <= nx188 AND nx189 ;
nx191 <= NOT nx130 ;
y(2) <= nx190 OR nx191 ;
nx4_dup_0_dup_193 <= NOT b(1) ;
nx194 <= NOT a(1) ;
nx195 <= nx4_dup_0_dup_193 OR nx194 ;
nx196 <= NOT c(1) ;
nx197 <= nx195 OR nx196 ;
nx198 <= NOT nx112 ;
nx130 <= nx197 OR nx198 ;
nx132 <= NOT c(0) ;
nx2 <= NOT a(0) ;
nx200 <= NOT b(0) ;
nx112 <= nx2 OR nx200 ;
nx142 <= NOT c(1) ;
nx202 <= NOT nx142 ;
nx203 <= NOT c(0) ;
nx143 <= nx202 AND nx203 ;
nx144 <= NOT a(1) ;
nx145 <= NOT b(0) ;
nx146 <= NOT b(1) ;
nx147 <= NOT a(0) ;
nx4_dup_0_dup_206 <= NOT nx146 ;
nx207 <= NOT nx147 ;
nx208 <= nx4_dup_0_dup_206 AND nx207 ;
nx209 <= NOT nx144 ;
nx210 <= NOT nx145 ;
nx10 <= nx209 AND nx210 ;
NOT_nx118 <= nx208 OR nx10 ;
nx212 <= NOT a(1) ;
nx213 <= NOT b(1) ;
nx107 <= nx212 OR nx213 ;
nx4_dup_0_dup_216 <= NOT nx112 ;
nx217 <= NOT nx107 ;
nx218 <= nx4_dup_0_dup_216 AND nx217 ;
nx219 <= NOT NOT_nx118 ;
nx220 <= nx218 OR nx219 ;
nx221 <= NOT nx143 ;
nx148 <= nx220 OR nx221 ;
nx4_dup_0_dup_224 <= NOT b(1) ;
nx225 <= NOT a(1) ;
nx226 <= nx4_dup_0_dup_224 AND nx225 ;
nx227 <= NOT nx142 ;
nx228 <= nx226 OR nx227 ;
nx229 <= NOT c(0) ;
nx149 <= nx228 OR nx229 ;
nx4_dup_0_dup_232 <= NOT a(1) ;
nx233 <= NOT nx144 ;
nx234 <= nx4_dup_0_dup_232 AND nx233 ;
nx235 <= NOT b(1) ;
nx236 <= nx235 AND nx233 ;
nx237 <= nx234 OR nx236 ;
nx238 <= NOT nx146 ;
nx14 <= nx4_dup_0_dup_232 AND nx238 ;
nx16 <= nx237 OR nx14 ;
nx18 <= nx235 AND nx238 ;
nx150 <= nx16 OR nx18 ;
nx241 <= NOT c(1) ;
nx4_dup_0_dup_242 <= NOT nx144 ;
nx243 <= nx241 AND nx4_dup_0_dup_242 ;
nx244 <= NOT nx146 ;
nx245 <= nx241 AND nx244 ;
nx151 <= nx243 OR nx245 ;
nx152 <= NOT nx112 ;
nx4_dup_0_dup_249 <= NOT nx151 ;
nx250 <= NOT c(0) ;
nx251 <= nx4_dup_0_dup_249 AND nx250 ;
nx252 <= NOT c(1) ;
nx253 <= nx4_dup_0_dup_249 AND nx252 ; nx254 <= nx251 OR nx253 ;
nx255 <= NOT nx152 ;
nx256 <= nx4_dup_0_dup_249 AND nx255 ;
nx153 <= nx254 OR nx256 ;
nx4_dup_0_dup_259 <= NOT nx150 ;
nx260 <= NOT nx153 ;
nx261 <= nx4_dup_0_dup_259 AND nx260 ;
nx262 <= NOT nx149 ;
nx263 <= nx261 OR nx262 ;
nx264 <= NOT nx148 ;
nx154 <= nx263 OR nx264 ;
nx155 <= c(1) AND c(0) ;
nx4_dup_0_dup_269 <= NOT nx154 ;
nx270 <= NOT nx155 ;
nx271 <= nx4_dup_0_dup_269 AND nx270 ;
nx272 <= NOT nx150 ;
nx273 <= nx4_dup_0_dup_269 AND nx272 ;
nx274 <= nx271 OR nx273 ;
nx275 <= NOT nx112 ;
nx276 <= nx4_dup_0_dup_269 AND nx275 ;
nx156 <= nx274 OR nx276 ;
y(1) <= NOT nx156 ;
nx278 <= NOT b(1) ;
nx279 <= NOT a(1) ;
nx127 <= nx278 AND nx279 ;
end beh ; |
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